MII Interface, Uart Interface Example | Intel IXP43X guide

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 5. UART Interface Example

					DB9
					Connector (Female)
	CTS0_N				1	1 DCD
	CTS0_N	OUT4			1	2 RX
UART Interface	RTS0_N	IN3			6	3 TX
	RTS0_N	IN3	IN1		2	3 TX
	RXDATA0	OUT1 OUT3			7	4 DTR
	TXDATA0	IN2	OUT2		3	5 GND
	TXDATA0	IN2			3	5 GND
Intel® IXP43X			IN4		8	6 DSR
Intel® IXP43X					4	6 DSR
Product Line of		RS-232		NC	9	7 RTS
Network Processors		RS-232			5	8 CTS
		Transceiver			5	8 CTS
						9 RI
						B4099 -005

3.5MII Interface

The IXP43X network processors support a maximum of two Ethernet MACs. Depending on the part number of the IXP43X network processors, various combinations can be used. Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for a detailed list of features that can be enabled depending upon your requirements.

All MACs contained in the NPEs are compliant to the IEEE 802.3 specification and handle flow control for the IEEE 802.3Q VLAN specification.

The Management Data Interface (MDI) supports a maximum of 32 PHY addresses. MDI signals are required to be connected to every PHY chip. Each PHY port is assign a unique address in the external PHY chip from 0 to 31, totaling a maximum of 32 PHY addresses. The maximum number of MACs supported by the IXP43X network processors is two.

The MII interface supports clock rates of 25 MHz for 100-Mbps operation or 2.5 MHz for 10-Mbps operation.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	29

Image 29

Intel IXP43X manual MII Interface, Uart Interface Example

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors April Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Chapter Name Description Content Overview Acronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term Explanation List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol Description USB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface Ethernet DDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface MII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C MII Interface Example Gpio Interface Design Notes Gpio Signal RecommendationsUSB Interface Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPDATA75 UTPOPDATA4UTPOPADDR40 Utpopfci Utpipfci ClavUtpipsoc ETHARXDATA30 Etharxclk UTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40 Device Connection HSS Interface HSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan Pciclkin PCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection Field Signal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description Field PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Signals Clock SignalsInput System Clock Clock Oscillator Recommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling § § PCB Overview Component PlacementGeneral Recommendations Component Selection Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations Crosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Group Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / Ddrcasn DDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations Sizea DDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement Banks DDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer Stackup Timing Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §