Intel IXP43X manual Type, Pull, Name, Description, Field, Down

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

		Type	Pull
	Name		Up/	Description
		Field
			Down
				UTOPIA Level 2 Mode of Operation:
				UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data
				from the processor to an ATM UTOPIA Level 2-compliant PHY.
UTP_OP_DATA[4] /		TRI	No	MII Mode of Operation:
ETHA_TXEN				Indicates that the PHY is being presented with nibbles on the MII interface.
				Asserted synchronously, with respect to ETHA_TXCLK, at the first nibble of the
				preamble, and remains asserted until all the nibbles of a frame are presented.
				This MAC does not contain hardware hashing capabilities that are local to the
				interface.
				UTOPIA Level 2 Mode of Operation:
UTP_OP_DATA[7:5]		TRI	No	UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data
				from the processor to an ATM UTOPIA Level 2-compliant PHY.
				Transmit PHY address bus. Used by the processor when operating in MPHY
				mode to poll and select a single PHY at any given time.
				When this interface/signal is enabled and is not being used in a system design,
UTP_OP_ADDR[4:0]		I/O	Yes	the interface/signal should be pulled high with a 10-KΩresistor. When this
				interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft
				fuse and is not being used in a system design, it is not required for any
				connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X
				Product Line of Network Processors Developer’s Manual.
				UTOPIA Level 2 Output data flow control input: Also known as the TXFULL/CLAV
				signal.
				Used to inform the processor, the ability of each polled PHY to receive a complete
				cell. For
				cell-level flow control in an MPHY environment, TxClav is an active high tri-
				stateable signal from the MPHY to ATM layer.
				The UTP_OP_FCI is connected to multiple MPHY devices. It sees the logic high
UTP_OP_FCI		I	Yes	generated by the PHY, one clock after the given PHY address is asserted and a
				full cell can be received by the PHY. The UTP_OP_FCI sees a logic low generated
				by the PHY one clock cycle, after the PHY address is asserted, and a full cell
				cannot be received by the PHY.
				When this interface/signal is enabled and is not being used in a system design,
				the interface/signal should be pulled high with a 10-KΩresistor. When this
				interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft
				fuse and is not being used in a system design, it is not required for any
				connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X
				Product Line of Network Processors Developer’s Manual.
				UTOPIA Level 2 Mode of Operation:
				UTOPIA Level 2 Receive clock input. Also known as UTP_RX_CLK.
				This signal is used to synchronize all UTOPIA Level 2-received inputs to the rising
				edge of the UTP_IP_CLK.
				MII Mode of Operation:
UTP_IP_CLK /		I	Yes	Externally supplied receive clock.
ETHA_RXCLK				• 25 MHz for 100 Mbps operation
				• 2.5 MHz for 10 Mbps
				This MAC interface does not contain hardware hashing capabilities that are local
				to the interface.
				When this interface/signal is enabled and is not being used in a system design,
				the interface/signal should be pulled high with a 10-KΩresistor.
††	Refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an
	interface.

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
38	Document Number: 316844; Revision: 001US