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Intel IXP43X manual SSP Interface, HSS Interface Example

Models: IXP43X

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Figure 11. HSS Interface Example

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 11. HSS Interface Example

Intel® IXP 43X		Vccp (3.3 V)
Product Line of	External Oscillator		10 KΩ
Network Processors			10 KΩ
GPIO_0
GPIO_1	Clock derived internally
	Clock derived internally
	from 3.6864 MHz
SSP _EXTCLK	or external oscilator
SSP _EXTCLK	33 MHz
	33 MHz	RESET_N	INT_ N
		RESET_N	INT_ N

SSP _SCLK

CLK

SSP _SFRM

CS_N

SSP_ TXD

D I

SSP_RXD

DO

SSP Interface

Vccp (3.3 V)

10 KΩ

HSS_TX_ FRAME0

HSS_TXDATA0

DTX

HSS_ TXCLK0

HSS_RXFRAME0

FSYNC

HSS_RXDATA0

RXD

HSS_ RXCLK0

PCLK

Clock derived from

SLIC/CODEC

HSS Interface

or external oscilator SLIC CODEC

512 KHz to

8.192 MHz

AFE

RJ11

B4108 -005

3.10SSP Interface

The IXP43X network processors have a Synchronous Serial Peripheral Interface (SSP) module. Its primary function is to provide connectivity between the Intel XScale® Processor and an external SSP interface.

The SSP module supports Texas Instruments synchronous serial protocol (SSP)*, Motorola serial peripheral interface (SPI)* and National Microwire*.

The clock rate can be selected from an internal, 3.6864-MHz source or external source fed at input pin SSP_EXTCLK. The clock can then be divided down anywhere from

7.2KHz to 1.84 MHz by setting bits 15:08 in SSP Control Register 0 (SSCR0). For

instructions on the SSP configuration register, refer to the Serial Clock Register (SCR) subsection in the Memory Controller chapter of the Intel® IXP43X Product Line of Network Processors Datasheet.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	43

Image 43

Intel IXP43X manual SSP Interface, HSS Interface Example

Contents

Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesApril April Intel IXP43X Product Line of Network ProcessorsIntroduction ContentsFigures Pad-to-Pad Clearance of Passive Components to a PGA or BGA TablesDDRII Data and Control Simulation Results DQ and DQS signals MAC Management Signal Recommendations NPE A and NPE CDDR Clock Timings April Revision HistoryApril Intel IXP43X Product Line of Network ProcessorsDocument Number 316844 Revision 001US 1.0 Introduction 1.1 Content OverviewIntel IXP400 Software Specification Update 1.2 Related Documentation1.3 Acronyms Intel IXP43X Product Line of Network Processors DatasheetTable 1. List of Acronyms and Abbreviations Sheet 2 of 1.4 Overview16 GPIO General Purpose Input Output Packaging 460-pin PBGA Figure 1. Intel IXP435 Network Processor Block Diagram 1.5 Typical Applications 2.1 System Architecture Description 2.0 System Architecture2.2 System Memory Map Memory Bus JTAGHeader ProcessorsSoft Fusible Features Sheet 1 of 3.1 Soft Fusible Features3.0 General Hardware Design Considerations Table 2. Signal Type DefinitionsSoft Fusible Features Sheet 2 of 3.2 DDRII/I SDRAM InterfaceDDRII/I SDRAM Interface Pin Description Sheet 1 of 3.2.1 Signal InterfaceDDRII/I SDRAM Interface Pin Description Sheet 2 of 3.2.2 DDRII/I SDRAM Initialization3.3 Expansion Bus 3.3.1 Signal InterfaceExpansion Bus Signal Recommendations Sheet 1 of Expansion Bus Signal Recommendations Sheet 2 of 3.3.2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 of Network Processors Developer’s Manual Boot/Reset Strapping Configuration Sheet 2 ofSetting Intel XScale Processor Operation Speed 3.3.3 8-Bit Device InterfaceApril 3.3.4 16-Bit Device InterfaceDocument Number 316844 Revision 001US Line of Network Byte Access16-Bit-Word Access Intel IXP43X Product16-Bit Device Intel Flash3.4 UART Interface 16-Bit-Word AccessUART Signal Recommendations 3.4.1 Signal Interface3 TX Connector Female1 DCD 2 RXbeing disabled without asserting a system reset 3.5.1 Signal Interface MIIMII NPE A Signal Recommendations MII NPE C Signal Recommendations Sheet 1 ofbeing disabled without asserting a system reset 3.5.2 Device Connection, MIIMII NPE C Signal Recommendations Sheet 2 of MAC Management Signal Recommendations - NPE A and NPE CIntel IXP43X 3.6 GPIO InterfaceNetwork Processors 10/100GPIO Signal Recommendations 3.6.1 Signal Interface3.7 USB Interface 3.6.2 Design NotesUSB Host Signal Recommendations 3.7.1 Signal InterfaceFigure 7. Common Mode Choke resistor USB RBIASPUSB RBIASN 22.6 Ω ±1 %3.8 UTOPIA Level 2 Interface 3.8.1 Signal InterfaceUTOPIA Level 2/MIIA Description TypePull NameDescription TypePull NameDescription TypePull NameProduct Line of 3.9 HSS Interface3.8.2 Device Connection Intel IXP43XHigh-Speed, Serial Interface 3.9.1 Signal Interface3.9.2 Device Connection being disabled without asserting a system resetFigure 11. HSS Interface Example 3.10 SSP Interface3.10.2 Device Connection 3.10.1 Signal InterfaceSynchronous Serial Peripheral Port Interface Processors 3.11 PCI InterfaceIntel IXP43X Product Line of NetworkPCI Controller Sheet 1 of 3.11.1 Signal InterfacePCI Controller Sheet 2 of 3.11.2 PCI Interface Block DiagramTable 18. PCI Host/Option Interface Pin Description Sheet 1 of 3.11.3 PCI Option InterfaceNetwork Processors Figure 13. PCI InterfaceName PCI Host/Option Interface Pin Description Sheet 2 ofType Option3.11.4 Design Notes 3.12 JTAG InterfacePCI Host/Option Interface Pin Description Sheet 3 of 3.13.2 Clock Oscillator 3.12.1 Signal Interface3.13.1 Clock Signals 3.13 Input System Clock33 KΩ Network3.13.3 Recommendations for Crystal Selection OSCINProcessors Datasheet 3.14 PowerPower Supply Processors Datasheet3.14.2 VCC Decoupling 3.14.5 Power Sequence3.14.6 Reset Timing 3.14.1 Decoupling Capacitance RecommendationsThe IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 4.2 General Recommendations 4.4 Component Placement4.0 General PCB Guide 4.1 PCB OverviewFigure 16. Component Placement on a PCB 4.5 Stack-Up SelectionInexpensive Manufactured by virtually all printed-circuit-board vendorsHigher cost More weight Manufactured by fewer vendors Poor routing density Uncontrolled signal trace impedanceLack of power/ground planes, resulting in unacceptable crosstalk Controlled-impedance traces Low-impedance power distributionFigure 18. 6-Layer Stackup Figure 17. 8-Layer Stackup5.1 Overview 5.0 General Layout and Routing Guide5.2 General Layout Guidelines 5.2.1 General Component Spacing VIAsFigure 19. Signal Changing Reference Planes Flush Via min Potential Bridge min Figure 20. Good Design Practice for VIA Hole PlacementFigure 21. Poor Design Practice for VIA Placement 25 mils min 25 mils min 25 mils minPBGA Package 5.2.2 Clock Signal ConsiderationsFigure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 5.2.4 USB V2.0 Considerations 5.2.3 MII Signal Considerations5.2.5 Crosstalk 5.2.6 EMI Design Considerations 5.2.8 Power and Ground Plane5.2.7 Trace Impedance Use at least one decoupling capacitor per power pin and place it as close as possible to the pin 6.1 Electrical Interface 6.0 PCI Interface Design Considerations6.2 Topology PCI Slot 6.3 Clock DistributionPCI Slot PCI SlotDriver 6.3.1 Trace Length LimitsPCI Devices Clock6.3.2 Routing Guidelines 6.3.3 Signal LoadingThis manual does not repeat all the guidelines that are already stated in the 7.1 Introduction 7.0 DDRII / DDRI SDRAMDescription DDRII/I Signal GroupsSignal Name GroupIXP43X DDR SDRAMProcessors Product Line of NetworkSupported DDRII 32-bit SDRAM Configurations Supported DDRI 32-bit SDRAM ConfigurationsSupported DDRI 16-bit SDRAM Configurations DDRIMPCRES DDRIR1 =387 Ω ±1 % resistor R 1 = 285 Ω ±1 % resistorFigure 28. DDR Clock Timing Waveform 7.3 DDRII OCD Pin Requirements7.3.1 Signal-Timing Analysis Figure 27. DDRII OCD Pin RequirementsCS10# CK DQS DQS # DQ Figure 29. DDR SDRAM Write TimingsFigure 30. DDR SDRAM Read Timings ADDR/CTRLFigure 31. DDR - Write Preamble/Postamble Duration DDRII-400 MHz Interface -- Signal TimingsSee Figure 29, “DDR SDRAM Write Timings” on page DDR II/I SDRAM Interface -- Signal Timings 7.3.2 Timing Relationships7.3.1.0.1 Printed Circuit Board Layer Stackup Figure 30 on page Table 32 on page Signal Package Lengths Sheet 1 ofTable 31 on page Table 32 on page Table 33 on pageGroup Signal Package Lengths Sheet 2 ofSignal Name Signal Name7.3.3.1 Clock Group 7.3.3 Routing GuidelinesSignal Package Lengths Sheet 3 of Figure 32. DDRII Clock Simulation Results CK Signals 7.3.3.2 Data and Control GroupsClock Signal Group Routing Guidelines Table 35. DDRII Data and Control Signal Group Routing Guidelines 22 ohmFigure 34. DDRII Command Simulation Results ADDRESS signals 7.3.3.3 Command Groups20ohm Table 35. DDRII Data and Control Signal Group Routing GuidelinesTable 36. DDRII Command Signal Group Routing Guidelines