Intel IXP43X manual DDRII OCD Pin Requirements, Signal-Timing Analysis, DDR Clock Timing Waveform

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

7.3DDRII OCD Pin Requirements

Figure 27 shows the requirement for the DDRRES1 and DDRRES2 pins.

Figure 27. DDRII OCD Pin Requirements

		DDRRES2
			Intel® IXP43X
		DDRRES1	Product Line
1 K Ω	40.2 Ω		of Network
		0. 1uF	Processors
resistor	resistor

Note: Since the OCD calibration function is not enabled, DDRRES2 must be pulled to ground with a 1-KΩresistor.

7.3.1Signal-Timing Analysis

Figure 28. DDR Clock Timing Waveform

V test

Vil(max )

Vih (min ) V ih (min)				V tch
	V il(max)	V il(max )	V test
				V tcl

T CH T CL

TC

Table 29.	DDR Clock Timings
				DDR-II 400		DDR-I 266
	Symbol		Parameter					Units	Notes
				Min	Max	Min	Max
	TF		DDR SDRAM clock Frequency		200		133	MHz
	TC		DDR SDRAM clock Cycle Time	5		7.5		ns	1
	TCH		DDR SDRAM clock High Time	2.15		3.37		ns	1
	TCL		DDR SDRAM clock Low Time	2.15		3.37		ns	1
	TCS		DDR SDRAM clock Period Stability		350		350	ps
	Tskew		DDR SDRAM clock skew for any
			differential clock pair (D_CK[2:0] -		100		100	ps
			D_CK_N[2:0])
	Notes:
	1.	See Figure 28, “DDR Clock Timing Waveform” on page 76
	2.	Vtest is nominally (0.5 * Vtch - Vtcl)

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
76	Document Number: 316844; Revision: 001US