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Intel® IXP43X Product Line of Network
7.3DDRII OCD Pin Requirements
Figure 27 shows the requirement for the DDRRES1 and DDRRES2 pins.
Figure 27. DDRII OCD Pin Requirements
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| DDRRES2 |
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| Intel® IXP43X |
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| DDRRES1 | Product Line |
1 K Ω | 40.2 Ω |
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0. 1uF | Processors | ||
resistor | resistor |
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Note: Since the OCD calibration function is not enabled, DDRRES2 must be pulled to ground with a
7.3.1Signal-Timing Analysis
Figure 28. DDR Clock Timing Waveform
V test
Vil(max )
Vih (min ) V ih (min) |
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| V tch |
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| V il(max) | V il(max ) |
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| V test | ||||
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| V tcl |
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T CH | T CL |
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TC
Table 29. | DDR Clock Timings |
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| Symbol |
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| Units | Notes |
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| Min | Max | Min | Max |
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| TF |
| DDR SDRAM clock Frequency |
| 200 |
| 133 | MHz |
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| TC |
| DDR SDRAM clock Cycle Time | 5 |
| 7.5 |
| ns | 1 |
| TCH |
| DDR SDRAM clock High Time | 2.15 |
| 3.37 |
| ns | 1 |
| TCL |
| DDR SDRAM clock Low Time | 2.15 |
| 3.37 |
| ns | 1 |
| TCS |
| DDR SDRAM clock Period Stability |
| 350 |
| 350 | ps |
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| Tskew |
| DDR SDRAM clock skew for any |
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| differential clock pair (D_CK[2:0] - |
| 100 |
| 100 | ps |
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| D_CK_N[2:0]) |
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| Notes: |
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| 1. | See Figure 28, “DDR Clock Timing Waveform” on page 76 |
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| 2. | Vtest is nominally (0.5 * Vtch - Vtcl) |
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Intel® IXP43X Product Line of Network Processors |
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HDG | April 2007 |
76 | Document Number: 316844; Revision: 001US |