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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 2. Example: Intel® IXP43X Product Line of Network Processors System Block Diagram

				JTAG
				Header
									DDR
Flash								CB[7:0]	DDR
Flash								CB[7:0]	DDR	AM
									S	AM
32 Mbyte			Expansion Bus						SDRAM
32 Mbyte									SDRAM
					Memory Bus			D[31:0]	16Mx4x16
		CS_N0							16Mx4x16
									16Mx4x16
									512 Mbyte
								BA[1:0]	SDRAM
								BA[1:0]	512 Mbyte
									512 Mbyte
									(Four Chips)
									Max 1 Gbyte
		D[15:0]						A[13:0]	(Four Chips)
		D[15:0]						A[13:0]	(Four Chips)
						RAS, CAS, WE, CS,CLK
Board		A[23:0]				DDRII/ISDRAM
Configuration
Reset Logic
			Intel® IXP43X Product				SSP		SLIC/CODEC or
			Intel® IXP43X Product				HSS 0		SLIC/CODEC or
				Line of Network			HSS 0		T1/E1/J1 Framer
				Line of Network
LCD/LED				Processors
Diagnostics	Buff						SSP		CODEC or
Display							SSP		CODEC or
Display									A/D
									A/D
	RS 232						UTOPIA Level 2		xDSL
	RS 232						UTOPIA Level 2		xDSL
DB9									xDSL
DB9	Serial Port 0								xDSL
	Serial Port 0
								Clock Buffer		PLL	OSC
RJ45	10/100						PCI Slots
Port 0	10/100	2-MII		PCI Bus				Ethernet	PCI
Port 0	PHYs	2-MII						Ethernet	PCI
RJ45	Up to 2 Ports							Clocks	Clock
RJ45
Port 1								5 V
	USB Host	USB v2.0						5 V
	USB Host	USB v2.0						3.3 V
	Connector							3.3 V	Power Supply
	USB Host	USB v2.0						2.5/1.8 V	Power Supply
	USB Host	USB v2.0		Transparent PCI Bridge				2.5/1.8 V
	Connector			Transparent PCI Bridge				1.3 V
								1.3 V
				cPCI Bus
				cPCI J2	cPCI J1
											B4835 -003
						§ §

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
16	Document Number: 316844; Revision: 001US

Image 16

Intel manual Intel IXP43X Product

Contents

Intel IXP43X Product Line of Network Processors Hardware Design Guidelines HDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Content Overview Chapter Name Description Related Documentation AcronymsList of Acronyms and Abbreviations Sheet 1 Term Explanation Overview List of Acronyms and Abbreviations Sheet 2 HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory Map Intel IXP43X Product Soft Fusible Features Signal Type DefinitionsSoft Fusible Features Sheet 1 Symbol Description Soft Fusible Features Sheet 2 USB Host Each USB can be Enable separatelyDDRII/I Sdram Interface Ethernet Signal Interface DDRII/I Sdram Interface Pin Description Sheet 1Type Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2 Expansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2Boot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 Setting Intel XScale Processor Operation Speed 3 8-Bit Device InterfaceIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz 4 16-Bit Device Interface Flash Interface 16-Bit Device Interface Uart Interface Flash Interface Example Uart Signal Recommendations MII Interface Uart Interface Example MII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII Gpio Interface MII Interface Example USB Interface Gpio Signal RecommendationsDesign Notes USB Host Signal Recommendations Name Type Pull Description Field Down Common Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down UTPOPDATA4 UTPOPDATA75UTPOPADDR40 Utpopfci Clav UtpipfciUtpipsoc ETHARXDATA30 Etharxclk UTPIPDATA5 UTPIPDATA6UTPIPDATA7 UTPIPADDR40 HSS Interface Device Connection High-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface Example PCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Pciintan Pciclkin Connect signal to same pin between PCI Parity Two devices PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection Field On the Option device, these signals are not Signal PCIREQN0 to one PCIREQN30 inputs to the HostPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description Field Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Clock Signals Clock SignalsInput System Clock Clock Oscillator Recommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description Power Sequence Reset TimingDecoupling Capacitance Recommendations VCC Decoupling § § Component Placement PCB OverviewGeneral Recommendations Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA USB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Electrical Interface Topology@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec PCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Ddrii / Ddri Sdram Introduction DDRII/I Signal Groups Group Signal Name DescriptionDrasn / Ddrrasn Dcasn / Ddrcasn DDR Sdram Supported Ddri 32-bit Sdram Configurations Supported Ddrii 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations Sizea Supported Ddrii 16-bit Sdram Configurations DDRII/DDRI Rcomp and Slew Resistances Pin RequirementsAddress Size Leaf Select Total Technology Arrangement Banks Ddrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum Units DDR II/I Sdram Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum UnitsTiming Relationships Printed Circuit Board Layer Stackup Group Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock Group Data and Control Groups Parameter Definition Ddrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Command Signal Group Routing Guidelines Signal Group Members § §