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Hardware Design
Table 17. | PCI Controller (Sheet 2 of 2) | ||||
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| Type | Pull |
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| Up/ | Recommendations | ||
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| Field | |||
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| Down |
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| Interrupt A. |
PCI_INTA_N |
| O/D | Yes | When this interface/signal is enabled and is used or not used in a system design, the | |
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| interface/signal should be pulled high with a |
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| Clock input. |
PCI_CLKIN |
| I | Yes | When this interface/signal is enabled and is not being used in a system design, the interface/ | |
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| signal should be pulled high with a |
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Notes: |
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1. | Features disabled/enabled by Soft Fuse must be done during the | ||||
| being disabled without asserting a system reset. | ||||
2. | Features disabled by a specific part number, do not require | ||||
| unconnected. |
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3. | Features enabled by a specific part number — and required to be Soft | ||||
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3.11.2PCI Interface Block Diagram
While using the IXP43X network processors in Master mode, the PCI module can interface to up to four PCI cards (devices) at 33 MHz. The limitation is due to load requirements to maintain signal integrity.
The
The IDSEL signals on the PCI slots can be connected to one of the PCI_AD lines, preferable to the higher order address signals. Reset support can be accomplished by using one of the GPIO pins to generate a reset or through an external decoder of the Expansion bus.
| Intel® IXP43X Product Line of Network Processors |
April 2007 | HDG |
Document Number: 316844; Revision: 001US | 47 |