Clock Signal Considerations | Intel IXP43X specs

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA

PBGA Package

60 mils min

60 mils min

60 mils min

B2268 -01

5.2.2Clock Signal Considerations

•Provide good return current paths for clock traces.

•Keep clock traces away from the edge of the board and any other high-speed devices or traces.

•Keep clock traces away from analog signals, including voltage reference signals.

•Clock signals should not cross over a split plane.

•Route clock signals in a single, internal layers and eliminate routing in multiple layers as much as possible.

•Do not route traces or vias under crystals or clock oscillators devices unless there is a plane between the trace and the component.

•Do not route parallel signal traces directly above or below clock traces unless there is a ground or at least a power plane separation between those layers.

•Route clock traces with a minimum number of vias.

•Space clock traces away from other signals three times the trace width on each side.

•Use guard traces when routing on top or bottom layers whenever possible. Guard traces must be connected to ground.

•Do not daisy-chain, instead use point-to-point clock distribution. Place a series termination resistor as close as possible to the source.

•Keep traces short to minimize reflections and signal degradation.

•Maintain control impedance for all clock traces, microstrip or stripline.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	63

Image 63

Intel IXP43X manual Clock Signal Considerations, Pad-to-Pad Clearance of Passive Components to a PGA or BGA

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors Intel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content Overview Term Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1 List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1 Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram Interface Name Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Type DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1 Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface Signal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio Interface Gpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40 ETHARXDATA30 Etharxclk ClavUtpipfci Utpipsoc UTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7 Device Connection HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 Pciintan Type Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Recommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations § § Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations MII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHz Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Dcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / Ddrrasn DDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram Configurations Technology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select Total DDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Printed Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing Relationships Signal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §