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Intel IXP43X R1 =387 Ω ±1 % resistor, R 1 = 285 Ω ±1 % resistor, Ddrimpcres, DDRCRES0, Ddrii

Models: IXP43X

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Supported DDRII 16-bit SDRAM Configurations

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 28.	Supported DDRII 16-bit SDRAM Configurations

				Address Size		Leaf Select		Total
DDR SDRAM		DDR SDRAM	# of					Total	Page
DDR SDRAM		DDR SDRAM	# of					Memory	Page
Technology		Arrangement	Banks			DDR_BA[1		Memory	Size
Technology		Arrangement	Banks	Row	Column	DDR_BA[1	DDR_BA[0]	Size	Size
				Row	Column	]	DDR_BA[0]	Size
						]

256 Mbit		16M x16	1	13	9	ADDR[24]	ADDR[23]	32MB	1KB

The DDR_RCOMP signal must be terminated through resistors specified in Figure 26. This allows the DDRII/I controller to make temperature and process adjustments.

7.2DDRII/DDRI RCOMP and Slew Resistances Pin Requirements

Figure 26 shows the requirements for the DDRII/DDRI RCOMP pin.

Figure 26. DDRII/DDRI RCOMP Pin External Resistor Requirements

	DDRI
	R1 =387Ω ±1% resistor
	OR
	DDRII
	R 1 = 285Ω ±1 % resistor
	DDRIMPCRES
	R1	Intel® IXP43X
	DDRCRES0	Intel® IXP43X
	DDRCRES0	Product Line of
		Network Processors
	R2
	DDRSLWCRES
	DDRI
	R2 =845Ω ±1% resistor
	OR
	DDRII
	R 2 = 825Ω ±1 % resistor

For example, when DDRI SDRAM is used, DDRIMPCRES is connected with 387Ω and DDRSLWCRES is connected with 845Ω resistor to DDRCRES0.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	75

Image 75

Intel R1 =387 Ω ±1 % resistor, R 1 = 285 Ω ±1 % resistor, Ddrimpcres, DDRCRES0, Ddrslwcres, Ddrii, Intel IXP43X

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsApril April Intel IXP43X Product Line of Network ProcessorsIntroduction ContentsFigures Pad-to-Pad Clearance of Passive Components to a PGA or BGA TablesDDRII Data and Control Simulation Results DQ and DQS signals MAC Management Signal Recommendations NPE A and NPE CDDR Clock Timings April Revision HistoryIntel IXP43X Product Line of Network Processors AprilDocument Number 316844 Revision 001US 1.0 Introduction 1.1 Content OverviewIntel IXP400 Software Specification Update 1.2 Related Documentation1.3 Acronyms Intel IXP43X Product Line of Network Processors DatasheetTable 1. List of Acronyms and Abbreviations Sheet 2 of 1.4 Overview16 GPIO General Purpose Input Output Packaging 460-pin PBGA Figure 1. Intel IXP435 Network Processor Block Diagram 1.5 Typical Applications 2.0 System Architecture 2.1 System Architecture Description2.2 System Memory Map Memory Bus JTAGHeader ProcessorsSoft Fusible Features Sheet 1 of 3.1 Soft Fusible Features3.0 General Hardware Design Considerations Table 2. Signal Type DefinitionsSoft Fusible Features Sheet 2 of 3.2 DDRII/I SDRAM InterfaceDDRII/I SDRAM Interface Pin Description Sheet 1 of 3.2.1 Signal InterfaceDDRII/I SDRAM Interface Pin Description Sheet 2 of 3.2.2 DDRII/I SDRAM Initialization3.3.1 Signal Interface 3.3 Expansion BusExpansion Bus Signal Recommendations Sheet 1 of 3.3.2 Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2 ofBoot/Reset Strapping Configuration Sheet 1 of Network Processors Developer’s Manual Boot/Reset Strapping Configuration Sheet 2 ofSetting Intel XScale Processor Operation Speed 3.3.3 8-Bit Device Interface3.3.4 16-Bit Device Interface AprilDocument Number 316844 Revision 001US Line of Network Byte Access16-Bit-Word Access Intel IXP43X Product16-Bit Device Intel Flash3.4 UART Interface 16-Bit-Word AccessUART Signal Recommendations 3.4.1 Signal Interface3 TX Connector Female1 DCD 2 RXbeing disabled without asserting a system reset 3.5.1 Signal Interface MIIMII NPE A Signal Recommendations MII NPE C Signal Recommendations Sheet 1 ofbeing disabled without asserting a system reset 3.5.2 Device Connection, MIIMII NPE C Signal Recommendations Sheet 2 of MAC Management Signal Recommendations - NPE A and NPE CIntel IXP43X 3.6 GPIO InterfaceNetwork Processors 10/100GPIO Signal Recommendations 3.6.1 Signal Interface3.7 USB Interface 3.6.2 Design NotesUSB Host Signal Recommendations 3.7.1 Signal InterfaceFigure 7. Common Mode Choke resistor USB RBIASPUSB RBIASN 22.6 Ω ±1 %3.8.1 Signal Interface 3.8 UTOPIA Level 2 InterfaceUTOPIA Level 2/MIIA Description TypePull NameDescription TypePull NameDescription TypePull NameProduct Line of 3.9 HSS Interface3.8.2 Device Connection Intel IXP43XHigh-Speed, Serial Interface 3.9.1 Signal Interface3.9.2 Device Connection being disabled without asserting a system resetFigure 11. HSS Interface Example 3.10 SSP Interface3.10.1 Signal Interface 3.10.2 Device ConnectionSynchronous Serial Peripheral Port Interface Processors 3.11 PCI InterfaceIntel IXP43X Product Line of NetworkPCI Controller Sheet 1 of 3.11.1 Signal InterfacePCI Controller Sheet 2 of 3.11.2 PCI Interface Block DiagramTable 18. PCI Host/Option Interface Pin Description Sheet 1 of 3.11.3 PCI Option InterfaceNetwork Processors Figure 13. PCI InterfaceName PCI Host/Option Interface Pin Description Sheet 2 ofType Option3.12 JTAG Interface 3.11.4 Design NotesPCI Host/Option Interface Pin Description Sheet 3 of 3.13.2 Clock Oscillator 3.12.1 Signal Interface3.13.1 Clock Signals 3.13 Input System Clock33 KΩ Network3.13.3 Recommendations for Crystal Selection OSCINProcessors Datasheet 3.14 PowerPower Supply Processors Datasheet3.14.2 VCC Decoupling 3.14.5 Power Sequence3.14.6 Reset Timing 3.14.1 Decoupling Capacitance RecommendationsThe IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 4.2 General Recommendations 4.4 Component Placement4.0 General PCB Guide 4.1 PCB OverviewFigure 16. Component Placement on a PCB 4.5 Stack-Up SelectionInexpensive Manufactured by virtually all printed-circuit-board vendorsHigher cost More weight Manufactured by fewer vendors Poor routing density Uncontrolled signal trace impedanceLack of power/ground planes, resulting in unacceptable crosstalk Controlled-impedance traces Low-impedance power distributionFigure 18. 6-Layer Stackup Figure 17. 8-Layer Stackup5.0 General Layout and Routing Guide 5.1 Overview5.2 General Layout Guidelines VIAs 5.2.1 General Component SpacingFigure 19. Signal Changing Reference Planes Flush Via min Potential Bridge min Figure 20. Good Design Practice for VIA Hole PlacementFigure 21. Poor Design Practice for VIA Placement 25 mils min 25 mils min 25 mils min5.2.2 Clock Signal Considerations PBGA PackageFigure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 5.2.3 MII Signal Considerations 5.2.4 USB V2.0 Considerations5.2.5 Crosstalk 5.2.8 Power and Ground Plane 5.2.6 EMI Design Considerations5.2.7 Trace Impedance Use at least one decoupling capacitor per power pin and place it as close as possible to the pin 6.0 PCI Interface Design Considerations 6.1 Electrical Interface6.2 Topology PCI Slot 6.3 Clock DistributionPCI Slot PCI SlotDriver 6.3.1 Trace Length LimitsPCI Devices Clock6.3.3 Signal Loading 6.3.2 Routing GuidelinesThis manual does not repeat all the guidelines that are already stated in the 7.1 Introduction 7.0 DDRII / DDRI SDRAMDescription DDRII/I Signal GroupsSignal Name GroupIXP43X DDR SDRAMProcessors Product Line of NetworkSupported DDRI 32-bit SDRAM Configurations Supported DDRII 32-bit SDRAM ConfigurationsSupported DDRI 16-bit SDRAM Configurations DDRIMPCRES DDRIR1 =387 Ω ±1 % resistor R 1 = 285 Ω ±1 % resistorFigure 28. DDR Clock Timing Waveform 7.3 DDRII OCD Pin Requirements7.3.1 Signal-Timing Analysis Figure 27. DDRII OCD Pin RequirementsCS10# CK DQS DQS # DQ Figure 29. DDR SDRAM Write TimingsFigure 30. DDR SDRAM Read Timings ADDR/CTRLDDRII-400 MHz Interface -- Signal Timings Figure 31. DDR - Write Preamble/Postamble DurationSee Figure 29, “DDR SDRAM Write Timings” on page 7.3.2 Timing Relationships DDR II/I SDRAM Interface -- Signal Timings7.3.1.0.1 Printed Circuit Board Layer Stackup Figure 30 on page Table 32 on page Signal Package Lengths Sheet 1 ofTable 31 on page Table 32 on page Table 33 on pageGroup Signal Package Lengths Sheet 2 ofSignal Name Signal Name7.3.3 Routing Guidelines 7.3.3.1 Clock GroupSignal Package Lengths Sheet 3 of 7.3.3.2 Data and Control Groups Figure 32. DDRII Clock Simulation Results CK SignalsClock Signal Group Routing Guidelines Table 35. DDRII Data and Control Signal Group Routing Guidelines 22 ohmFigure 34. DDRII Command Simulation Results ADDRESS signals 7.3.3.3 Command Groups20ohm Table 35. DDRII Data and Control Signal Group Routing GuidelinesTable 36. DDRII Command Signal Group Routing Guidelines