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Intel IXP43X manual Routing Guidelines, Signal Loading

Models: IXP43X

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

6.3.2Routing Guidelines

It is recommended to route signals with respect to an adjacent ground plane. If routing signals over power planes, ensure that the signals are referenced to a single power plane voltage level and not multiple levels. For example, you can route signals over a

3.3V plane or a 5 V plane, but do not route the same signal over both planes. If signals are routed over split planes, you must connect the splitting planes with 0.01 µF, high-speed capacitors near the signal crossing the split. The capacitors should not be placed more than 0.25 inches from the point at which the signals cross the split.

This manual does not repeat all the guidelines that are already stated in the

PCI Local Bus Specification, Rev. 2.2. Refer to the specification when designing a motherboard or an expansion card.

6.3.3Signal Loading

Shared PCI signals must be limited to one load on each of the PCI slots. Any violation of expansion board or add-on device trace length or loading limits compromises system-signal integrity.

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Intel® IXP43X Product Line of Network Processors
HDG	April 2007
70	Document Number: 316844; Revision: 001US

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Intel IXP43X manual Routing Guidelines, Signal Loading

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Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesApril Intel IXP43X Product Line of Network Processors AprilContents IntroductionFigures MAC Management Signal Recommendations NPE A and NPE C TablesDDRII Data and Control Simulation Results DQ and DQS signals Pad-to-Pad Clearance of Passive Components to a PGA or BGADDR Clock Timings Revision History AprilApril Intel IXP43X Product Line of Network ProcessorsDocument Number 316844 Revision 001US 1.1 Content Overview 1.0 IntroductionIntel IXP43X Product Line of Network Processors Datasheet 1.2 Related Documentation1.3 Acronyms Intel IXP400 Software Specification Update1.4 Overview Table 1. List of Acronyms and Abbreviations Sheet 2 of16 GPIO General Purpose Input Output Packaging 460-pin PBGA Figure 1. Intel IXP435 Network Processor Block Diagram 1.5 Typical Applications 2.1 System Architecture Description 2.0 System Architecture2.2 System Memory Map Processors JTAGHeader Memory BusTable 2. Signal Type Definitions 3.1 Soft Fusible Features3.0 General Hardware Design Considerations Soft Fusible Features Sheet 1 of3.2 DDRII/I SDRAM Interface Soft Fusible Features Sheet 2 of3.2.1 Signal Interface DDRII/I SDRAM Interface Pin Description Sheet 1 of3.2.2 DDRII/I SDRAM Initialization DDRII/I SDRAM Interface Pin Description Sheet 2 of3.3 Expansion Bus 3.3.1 Signal InterfaceExpansion Bus Signal Recommendations Sheet 1 of Expansion Bus Signal Recommendations Sheet 2 of 3.3.2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 of Boot/Reset Strapping Configuration Sheet 2 of Network Processors Developer’s Manual3.3.3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedApril 3.3.4 16-Bit Device InterfaceDocument Number 316844 Revision 001US Intel IXP43X Product Byte Access16-Bit-Word Access Line of Network16-Bit-Word Access Intel Flash3.4 UART Interface 16-Bit Device3.4.1 Signal Interface UART Signal Recommendations2 RX Connector Female1 DCD 3 TXMII NPE C Signal Recommendations Sheet 1 of 3.5.1 Signal Interface MIIMII NPE A Signal Recommendations being disabled without asserting a system resetMAC Management Signal Recommendations - NPE A and NPE C 3.5.2 Device Connection, MIIMII NPE C Signal Recommendations Sheet 2 of being disabled without asserting a system reset10/100 3.6 GPIO InterfaceNetwork Processors Intel IXP43X3.6.2 Design Notes 3.6.1 Signal Interface3.7 USB Interface GPIO Signal Recommendations3.7.1 Signal Interface USB Host Signal RecommendationsFigure 7. Common Mode Choke 22.6 Ω ±1 % USB RBIASPUSB RBIASN resistor3.8 UTOPIA Level 2 Interface 3.8.1 Signal InterfaceUTOPIA Level 2/MIIA Name TypePull DescriptionName TypePull DescriptionName TypePull DescriptionIntel IXP43X 3.9 HSS Interface3.8.2 Device Connection Product Line ofbeing disabled without asserting a system reset 3.9.1 Signal Interface3.9.2 Device Connection High-Speed, Serial Interface3.10 SSP Interface Figure 11. HSS Interface Example3.10.2 Device Connection 3.10.1 Signal InterfaceSynchronous Serial Peripheral Port Interface Line of Network 3.11 PCI InterfaceIntel IXP43X Product Processors3.11.1 Signal Interface PCI Controller Sheet 1 of3.11.2 PCI Interface Block Diagram PCI Controller Sheet 2 ofFigure 13. PCI Interface 3.11.3 PCI Option InterfaceNetwork Processors Table 18. PCI Host/Option Interface Pin Description Sheet 1 ofOption PCI Host/Option Interface Pin Description Sheet 2 ofType Name3.11.4 Design Notes 3.12 JTAG InterfacePCI Host/Option Interface Pin Description Sheet 3 of 3.13 Input System Clock 3.12.1 Signal Interface3.13.1 Clock Signals 3.13.2 Clock OscillatorOSCIN Network3.13.3 Recommendations for Crystal Selection 33 KΩProcessors Datasheet 3.14 PowerPower Supply Processors Datasheet3.14.1 Decoupling Capacitance Recommendations 3.14.5 Power Sequence3.14.6 Reset Timing 3.14.2 VCC DecouplingThe IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 4.1 PCB Overview 4.4 Component Placement4.0 General PCB Guide 4.2 General RecommendationsManufactured by virtually all printed-circuit-board vendors 4.5 Stack-Up SelectionInexpensive Figure 16. Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Poor routing density Uncontrolled signal trace impedanceLack of power/ground planes, resulting in unacceptable crosstalk Higher cost More weight Manufactured by fewer vendorsFigure 17. 8-Layer Stackup Figure 18. 6-Layer Stackup5.1 Overview 5.0 General Layout and Routing Guide5.2 General Layout Guidelines 5.2.1 General Component Spacing VIAsFigure 19. Signal Changing Reference Planes 25 mils min 25 mils min 25 mils min Figure 20. Good Design Practice for VIA Hole PlacementFigure 21. Poor Design Practice for VIA Placement Flush Via min Potential Bridge minPBGA Package 5.2.2 Clock Signal ConsiderationsFigure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 5.2.4 USB V2.0 Considerations 5.2.3 MII Signal Considerations5.2.5 Crosstalk 5.2.6 EMI Design Considerations 5.2.8 Power and Ground Plane5.2.7 Trace Impedance Use at least one decoupling capacitor per power pin and place it as close as possible to the pin 6.1 Electrical Interface 6.0 PCI Interface Design Considerations6.2 Topology PCI Slot 6.3 Clock DistributionPCI Slot PCI SlotClock 6.3.1 Trace Length LimitsPCI Devices Driver6.3.2 Routing Guidelines 6.3.3 Signal LoadingThis manual does not repeat all the guidelines that are already stated in the 7.0 DDRII / DDRI SDRAM 7.1 IntroductionGroup DDRII/I Signal GroupsSignal Name DescriptionProduct Line of Network DDR SDRAMProcessors IXP43XSupported DDRII 32-bit SDRAM Configurations Supported DDRI 32-bit SDRAM ConfigurationsSupported DDRI 16-bit SDRAM Configurations R 1 = 285 Ω ±1 % resistor DDRIR1 =387 Ω ±1 % resistor DDRIMPCRESFigure 27. DDRII OCD Pin Requirements 7.3 DDRII OCD Pin Requirements7.3.1 Signal-Timing Analysis Figure 28. DDR Clock Timing WaveformADDR/CTRL Figure 29. DDR SDRAM Write TimingsFigure 30. DDR SDRAM Read Timings CS10# CK DQS DQS # DQFigure 31. DDR - Write Preamble/Postamble Duration DDRII-400 MHz Interface -- Signal TimingsSee Figure 29, “DDR SDRAM Write Timings” on page DDR II/I SDRAM Interface -- Signal Timings 7.3.2 Timing Relationships7.3.1.0.1 Printed Circuit Board Layer Stackup Table 32 on page Table 33 on page Signal Package Lengths Sheet 1 ofTable 31 on page Figure 30 on page Table 32 on pageSignal Name Signal Package Lengths Sheet 2 ofSignal Name Group7.3.3.1 Clock Group 7.3.3 Routing GuidelinesSignal Package Lengths Sheet 3 of Figure 32. DDRII Clock Simulation Results CK Signals 7.3.3.2 Data and Control GroupsClock Signal Group Routing Guidelines 22 ohm Table 35. DDRII Data and Control Signal Group Routing GuidelinesTable 35. DDRII Data and Control Signal Group Routing Guidelines 7.3.3.3 Command Groups20ohm Figure 34. DDRII Command Simulation Results ADDRESS signalsTable 36. DDRII Command Signal Group Routing Guidelines