Instruction List (12)

S1C63000 Core CPU

Classification

8/16-bit transfer and operation

Mnemonic

Opcode

Operand

LDB

%BA,imm8

 

%BA,[%X]+

 

%BA,[%Y]+

LDB

%XL,%BA

 

%XL,imm8

 

%XH,%BA

LDB

%YL,%BA

 

%YL,imm8

 

%YH,%BA

LDB

%EXT,%BA

 

%EXT,imm8

Basic function

BA imm8 A [X], B [X+1], X X+2 A [Y], B [Y+1], Y Y+2 XL BA XL imm8 XH BA YL BA YL imm8 YH BA EXT BA EXT imm8

Extended function

Clk

 

Flags

 

Symbol

(when "LDB %EXT, imm8" is executed)

E

I

C

Z

 

 

1

0

,@h

2

0

2

0

1

0

X imm16 (imm8 set in EXT is used as high-order 8 bits)

1

0

,@l

1

0

1

0

Y imm16 (imm8 set in EXT is used as high-order 8 bits)

1

0

,@l

1

0

1

1

1

1

,@l,@h

 

 

 

 

 

 

@rh,@xh

 

LDB

%SP1,%BA

 

 

%SP2,%BA

 

LDB

[%X]+,%BA

 

 

[%X]+,imm8

 

LDB

[%Y]+,%BA

 

ADD

%X,%BA

 

 

%X,sign8

 

 

%Y,%BA

 

 

%Y,sign8

 

CMP

%X,imm8

 

 

%Y,imm8

 

INC

%SP1

 

 

%SP2

 

DEC

%SP1

 

 

%SP2

Stack

PUSH

%A

operation

 

%B

 

 

%F

 

 

%X

 

 

%Y

 

POP

%A

 

 

%B

 

 

%F

 

 

%X

 

 

%Y

SP1 BA SP2 BA [X] A, [X+1] B, X X+2

[X]i3~0, [X+1] i7~4, X X+2

[Y]A, [Y+1] B, Y Y+2

X X+BA X X+sign8 (sign8=-128~127) Y Y+BA Y Y+sign8 (sign8=-128~127)X-imm8 (imm8=0~255) Y-imm8 (imm8=0~255) SP1 SP1+1 SP2 SP2+1 SP1 SP1-1 SP2 SP2-1[SP2-1]A, SP2 SP2-1[SP2-1]B, SP2 SP2-1[SP2-1]F, SP2 SP2-1([(SP1-1)4+3]~[(SP1-1)4]) X, SP1 SP1-1 ([(SP1-1)4+3]~[(SP1-1)4]) Y, SP1 SP1-1 A [SP2], SP2 SP2+1 B [SP2], SP2 SP2+1 F [SP2], SP2 SP2+1 X ([SP14+3]~[SP14]), SP1 SP1+1 Y ([SP14+3]~[SP14]), SP1 SP1+1

1

0

1

0

2

0

2

0

,@l,@h

2

0

1

0

X X+imm16 (imm8 set in EXT is used as high-order 8 bits)

1

0

,@l

1

0

Y Y+imm16 (imm8 set in EXT is used as high-order 8 bits)

1

0

,@l

X-imm16 (imm8 set in EXT is used as high-order 8 bits)

1

0

↔ ↔

,@l

Y-imm16 (imm8 set in EXT is used as high-order 8 bits)

1

0

↔ ↔

,@l

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

↔ ↔ ↔ ↔

1

0

1

0

Remarks