Fluke 2625A, 2635A 2A-42.Digital I/O, 2A-43.Digital Input Threshold, 2A-44.Digital Input Buffers

Theory of Operation (2635A) 2A

Detailed Circuit Description

2A-42.Digital I/O

The following paragraphs describe the Digital Input Threshold, Digital Input Buffers, Digital and Alarm Output Drivers, Totalizer Input, and External Trigger Input circuits.

2A-43.Digital Input Threshold

The Digital Input Threshold circuit sets the input threshold level for the Digital Input Buffers and the Totalizer Input. A fixed value voltage divider (A1R36, A1R37) and a unity gain buffer amplifier (A1U8) are the main components in this circuit. The voltage from the divider (approximately +1.4V dc) is then buffered by A1U8, which sets the input threshold. Capacitor A1C29 filters the divider voltage at the input of A1U8.

2A-44.Digital Input Buffers

Since the eight Digital Input Buffers are identical in design, only components used for Digital Input 0 are referenced in this description. If the Digital Output Driver (A1U17-

12)is off, the input to the Digital Input Buffer is determined by the voltage level at A1J5-10. If the Digital Output Driver is on, the input of the Digital Input Buffer is the voltage at the output of the Digital Output Driver.

The Digital Input Threshold circuit and resistor network A1Z1 determine the input threshold voltage and hysteresis for inverting comparator A1U3. The inverting input of the comparator (A1U3-13) is protected by a series resistor (A1Z3) and diode A1CR14. A negative input clamp circuit (A1Q9, A1Z2, and A1CR17) sets a clamp voltage of approximately +0.7V dc for the protection diodes of all Digital Input Buffers. A negative input voltage at A1J5-10 causes A1CR14 to conduct current, clamping the comparator input A1U3-13 at approximately 0V dc.

The input threshold of +1.4V dc and a hysteresis of +0.5V dc are used for all Digital Input Buffers. When the input of the Digital Input Buffer is greater than approximately +1.25V dc, the output of the inverting comparator is low. When the input then drops below about +0.75V dc, the output of the inverting comparator goes high.

2A-45.Digital and Alarm Output Drivers

Since the 12 Digital Output and Alarm Output Drivers are identical in design, the following example description references only the components that are used for Alarm Output Driver 0.

The Microprocessor controls the state of Alarm Output Driver 0 by writing to the Alarm Output register in the FPGA (A1U25) to set the level of output A1U25-63. When A1U25-63 is set high, the output of the open-collector Darlington driver (A1U17-16) sinks current through current-limiting resistor A1R62. When A1U25-63 is set low, the driver output turns off and is pulled up by A1Z2 and/or the voltage of the external device that the output is driving. If the driver output is driving an external inductive load, the internal flyback diode (A1U17-9) conducts the energy into MOV A1RV1 to keep the driver output from being damaged by excessive voltage. Capacitor A1C58 ensures that the instrument meets electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance requirements.

2A-46.Totalizer Input

The Totalizer Input circuit consists of Input Protection, a Digital Input Buffer circuit, and a Totalizer Debouncing circuit. The Digital Input Buffer for the totalizer is protected from electrostatic discharge (ESD) damage by A1R49 and A1C43. Refer to the detailed description of the Digital Input Buffer circuit for more information.

2A-19