7.6 Bus Phases
Unless a parity error is detected, the TARG can execute the received message immediately after its reception. If a parity error is detected, the TARG ignores that part of the message which has been received after the detection of the parity error. Suppose that when the INIT retransmits a series of messages in the MESSAGE OUT phase, the TARG has already executed some messages. In this event, the TARG must handle the received messages so that no logical contradiction will occur (for example, the TARG must ignore received messages that have already been executed).
If the TARG receives all message information normally without detecting a parity error, the TARG must enter an INFORMATION TRANSFER phase other than a MESSAGE OUT phase and must send at least one byte of information in order to advise the INIT that message transfer retry is unnecessary. However, for some types of message (ABORT and BUS DEVICE RESET, for example), the TARG can report the normal completion of message reception by entering a BUS FREE phase.
7.6.10 Signal requirements concerning transition between bus phases
When the SCSI bus is at a midpoint between two INFORMATION TRANSFER phases (during the period of bus phase transition), interface signals must satisfy the requirements below.
1)The status of the BSY, SEL, REQ, and ACK signals must not change.
2)The status of the ATN and RST signals can change within the range determined by the ATTENTION condition (see Subsection 7.7.1) or RESET condition (see Subsection 7.7.2).
3)The status of the C/D, I/O and MSG signals and the DATA BUS (DBn) can change. However, the direction of data transfer over the DATA BUS must satisfy the following rule. (See Figure 7.18.)
•When changing the direction of transfer from Out (from INIT to TARG) to In (from TARG to INIT), the TARG must begin to drive the data bus (DBn) at least Data Release Delay + Bus Settle Delay after making the I/O signal true. The INIT must stop driving the data bus within Data Release Delay after the I/O signal becomes true.
•When changing the direction of transfer from In (from TARG to INIT) to Out (from INIT to TARG), the TARG must stop driving the data bus (DBn) within Deskew Delay after making the I/O signal false.
