MVME2400-Series Single Board Computer Installation and Use
Restricted Rights Legend
Model
Memory Handles
Document Terminology
Safety Summary Safety Depends On You
Equipment. Use extreme caution when handling, testing,
Page
Page
Page
Contents
Functional Description
Programming the MVME240x
Glossary
List of Figures
Xiv
List of Tables
Xvi
Introduction
MVME240x Description
MVME240x Module
MVME240x Models
PMCspan Expansion Mezzanine
PCI Mezzanine Cards PMCs
PMCspan Models
Expansion Module Description
Overview of Start-Up Procedures
VMEsystem Enclosure
System Console Terminal
Start-Up Overview
PMCspan
Installing the MVME240x Hardware Status Indicators
MVME240x
Unpacking the MVME240x Hardware
Preparing the MVME240x Hardware
Preparing and Installing the MVME2400-Series Module
ConnectorsHeaders,MFVME240xigure 1-1.Switches, LEDs
MVME240xPreparing theHardware
Setting the VMEbus System Controller Selection Header J9
General-Purpose Software-Readable Header
PMCs
PMCspan
Installing the MVME240x Hardware
ESD Precautions
Preparing and Installing the MVME2400-Series Module
Typical Single-width PMC Module Placement on MVME240x
Primary PMCspan
PMCspan-002 Installation on an MVME240x
Secondary PMCspan
PMCspan-010 Installation onto a PMCspan-002/MVME240x
Preparing and Installing the MVME2400-Series Module
MVME240x
Preparing and Installing the MVME2400-Series Module
Installation Considerations
Preparing and Installing the MVME2400-Series Module
Applying Power
Operating Instructions
Switches
MVME240x
ABT S1
RST S2
Status Indicators
10/100 Baset Port
PMC2 DS3
PMC1 DS4
Debug Port
MVME240x
MVME240x Debug Port Configuration
PMC Slots
PCI Mezzanine Card PMC Slot
PMCspan
Feature Description
Features
MVME240x Features
VME I/O
Features
MPC750 Processor
Block Diagram
General Description
MVME240x Block Diagram
Power Requirements
L2 Cache
Hawk System Memory Controller SMC/PCI Host Bridge PHB Asic
PCI Originated Latency Matrix
PCI Bus Latency
PCI Originated Bandwidth Matrix
PPC60x Originated Latency Matrix
PPC Bus Latency
PPC60x Originated Bandwidth Matrix
Assumptions
Clock Ratios and Operating Frequencies
PPC60x Originated
Sdram Memory
PCI Originated
Sdram Latency
X Bus to Sdram Access Timing 100MHz/PC100 SDRAMs
Access Time Comments TB1-tB2-tB3-tB4
X Bus to Sdram Access Timing 100MHz/PC100 SDRAMs
Timing Definitions for PPC Bus to Sdram Access
Functional Description
Flash Memory
ROM/Flash Performance
Total
1st Beat 2nd Beat 3rd Beat 4th Beat Clocks Bits
12. PPC Bus to ROM/Flash Access Timing 50ns @ 100MHz
1st Beat 2nd Beat 3rd Beat 4th Beat Bits
Ethernet Interface
PCI Mezzanine Card PMC Interface
PMC Slot 1 Single-Width PMC
PCI Expansion
PMC Slot 2 Single-Width PMC
PMC Slots 1 and 2 Double-Width PMC
VMEbus Interface
Asynchronous Debug Port
PCI-ISA Bridge PIB Controller
Real-Time Clock/NVRAM/Timer Function
PCI Host Bridge PHB
Interrupt Controller Mpic
Programmable Timers
Interval Timers
16/32-Bit Timers
Page
Programming the MVME240x
Memory Maps
Processor Bus Memory Map
Default Processor Memory Map
Processor Default View of the Memory Map
PCI Local Bus Memory Map
VMEbus Memory Map
Programming Considerations
PCI Arbitration
VMEbus Master Mapping
PCI Bus Request PCI Masters
Interrupt Handling
PCI Arbitration Assignments
MVME240x Interrupt Architecture
Sources of Reset
DMA Channels
Classes of Reset and Effectiveness
Asic
PCI Domain
Endian Issues
Processor/Memory Domain
Role of the Universe Asic
VMEbus Domain
Page
PPCBug Overview
PPCBug Basics
PPCBug
PPCBug Implementation
MPU, Hardware, and Firmware Initialization
Memory Requirements
PPCBug
Using PPCBug
Debugger Commands
Debugger Commands
Command Description
Gevedit
NAB
Diagnostic Tests
Time
PPC4-Bug prompt
Diagnostic Test Groups
Test Group Description
Modifying the Environment
Overview
Cnfg Configure Board Information Block
Configuring the PPCBug Parameters
ENV Set Environment
Remote Start Method Switch G/M/B/N = B?
Select the identifier. Default =
Nvram Bootlist GEV.fw-boot-path Boot Enable Y/N = N?
Default = $00
ROM Boot Enable Y/N = N?
Network Auto Boot Enable Y/N = N?
Nvram
ROM Next Access Length 0 15 = 0?
Configuring the VMEbus Interface
PCI Slave Image 0 Control = 00000000?
PCI Slave Image 2 Bound Address Register = 22000000?
VMEbus Slave Image 1 Base Address Register = 00000000?
VMEbus Slave Image 3 Translation Offset = 00000000?
Document Title Publication Number
Motorola Computer Group Documents
Table A-1. Motorola Computer Group Documents
Document Title and Source Publication Number
Manufacturers’ Documents
Table A-2. Manufacturers’ Documents
Ordering Related Documentation
Table A-2. Manufacturers’ Documents
Related Specifications
Table A-3. Related Specifications
Related Specifications
ANSI/EIA-232-D
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Characteristics Specifications
Specifications
Table B-1. MVME240x Specifications
PMC I/O
Cooling Requirements
EMC Regulatory Compliance
Connector Location
Pin Assignments
Row Z Row a Row B Row C Row D
VMEbus Connector P1
Table C-1. P1 VMEbus Connector Pin Assignments
Connector Pin Assignments
VMEbus Connector P2
Table C-2. P2 Connector Pin Assignment
VPC
Serial Port Connector Debug J2
Ethernet Connector 10BASET J3
Table C-3. Debug J2Connector Pin Assignments
Table C-4 /100 Baset J3 Connector Pin Assignments
CPU Debug Connector J1
Table C-5. Debug Connector Pin Assignments
PD0 PD2 PD4 PD6 PD8
100 102 104 106 108 110 112 114
+3.3V
Table C-5. Debug Connector Pin Assignments
PCI Expansion Connector J6
Table C-6. J6 PCI Expansion Connector Pin Assignments
PAR
PAR64
J11 J12
PCI Mezzanine Card Connectors J11 through J14
Table C-7. J11 J12 PMC1 Connector Pin Assignments
Table C-8. J13 J14 PMC1 Connector Pin Assignments
J13 J14
PMC143 P2-C22 PMC144 P2-A22
J21 J22
PCI Mezzanine Card Connectors J21 through J24
Table C-9. J21 and J22 PMC2 Connector Pin Assignments
Table C-10. J23 and J24 PMC2 Connector Pin Assignments
J23 J24
PMC231 P2-D21 PMC232 P2-Z21
Solving Startup Problems
Table D-1. Troubleshooting MVME240x Modules
Solving Startup Problems
Troubleshooting the MVME240x
Troubleshooting Procedure Complete
Glossary
Abbreviations, Acronyms, and Terms to Know
O S S a R Y
Compact Disk Read-Only Memory
Dynamic Random Access Memory. a memory technology that is
Fiber Distributed Data Interface. a network based on the use
High
Ultra 603/Ultra 604 system board. It provides the necessary
Operating System. The software that manages the computer
IBM
Random-Access Memory. The temporary memory that a computer
Single Inline Memory Module. a small circuit board with RAM
UltraViolet
EXtended Graphics Array. An improved IBM VGA monitor
GL-14
Index
Dram
IN-3
PCI bus 3-4,3-23,3-26,4-3,4-6 PCI bus latency
PHB
Romnal
IN-7
Index
Cover Pages 1/8 spine
86 100 pages 5/16 spine
