Index

I

N D E X

lowercase 5-12

M

M48T59/T559 3-27manufacturers’ documents A-2memory available B-1memory map

PCI local bus 4-2, 4-3memory maps

MVME240x 4-1VMEbus 4-3

memory size 6-11Memory Size Enable 6-11memory sizes

SDRAM 3-14

Motorola Computer Group documents A-1MPC750 processor 3-4

MPIC (MultiProcessor Interrupt Controler) 3-28

MPU initialization 5-3MPU specifications B-1MVME240x

board layout 1-9

EMC regulatory compliance B-4specifications B-1

MVME240x

cooling requirements B-3installing 1-21

LEDs 2-4programming 4-1regulatory compliance B-4status indicators 2-4

MVME240x features 3-1

MVME240x VME Processor Module 1-2

N

Negate VMEbus SYSFAIL* Always 6-5NETboot enable 6-9

Network Auto Boot Controller 6-10Network Auto Boot enable 6-9NIOT debugger command

using 6-10

Non-Volatile RAM (NVRAM) 6-1, 6-3NVRAM (BBRAM) configuration area 3-22NVRAM Bootlist 6-6

O

operating parameters 6-1operation

parameter (Auto Boot Abort Delay) 6-8parameter (Auto Boot Controller) 6-8parameter (Auto Boot Default String)

6-8

parameter (Auto Boot Device) 6-8parameter (Auto Boot Partition Number)

6-8

parameter (L2 Cache Parity Enable) 6-12

parameter (Memory Size) 6-11parameter (Negate VMEbus SYSFAIL*

Always) 6-5

parameter (Network Auto Boot Control- ler) 6-10

parameter (NVRAM Bootlist) 6-6parameter (Primary SCSI Bus Negotia-

tions) 6-5

parameter (Primary SCSI Data Bus Width) 6-5

parameter (ROM Boot Enable) 6-8parameter (SCSI bus reset on debugger

startup) 6-5

parameter (Secondary SCSI identifier) 6-5

P

P1 and P2 1-23

P1 and P2 connectors 1-2, C-2parallel port 4-8

parity 1-12, 2-5PC16550 2-5

PCI bus 3-4,3-23,3-26,4-3,4-6 PCI bus latency 3-8

PCI expansion 3-23, 3-24

connector description/location 3-24

IN-4

Computer Group Literature Center Web Site

Page 172
Image 172
Motorola MVME2400 manual PCI bus 3-4,3-23,3-26,4-3,4-6 PCI bus latency