Motorola MVME2400 manual Sdram Latency, X Bus to Sdram Access Timing 100MHz/PC100 SDRAMs

Block Diagram

consisting of 18 devices that total 128Mbytes. With 128Mbit (4bit data) devices, the block contains 256Mbytes. When populated, these blocks appear as Block A and Block B to the Hawk.

Refer to the MVME2400-Series VME Processor Module Programmer’s Reference Guide for additional information and programming details.

SDRAM Latency

The following table shows the performance summary for SDRAM when operating at 100MHz using PC100 SDRAM with a CAS_latency of 2. The figure on the next page defines the times that are specified in the table.

Table 3-9. 60x Bus to SDRAM Access Timing (100MHz/PC100 SDRAMs)

ACCESS TYPE	Access Time	Comments
	(tB1-tB2-tB3-tB4)
4-Beat Read after idle,	10-1-1-1
SDRAM Bank Inactive
4-Beat Read after idle,	12-1-1-1
SDRAM Bank Active - Page Miss
4-Beat Read after idle,	7-1-1-1
SDRAM Bank Active - Page Hit
4-Beat Read after 4-Beat Read,	5-1-1-1
SDRAM Bank Active - Page Miss
4-Beat Read after 4-Beat Read,	2.5-1-1-1	2.5-1-1-1 is an average of 2-
SDRAM Bank Active - Page Hit		1-1-1 half of the time and 3-
		1-1-1 the other half.
4-Beat Write after idle,	4-1-1-1
SDRAM Bank Active or Inactive
4-Beat Write after 4-Beat Write,	6-1-1-1
SDRAM Bank Active - Page Miss

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