Motorola MVME2400 manual PCI Originated Bandwidth Matrix

Block Diagram

			Table 3-4. PCI Originated Bandwidth Matrix
		First 2			First 4			First 6		Continuous		3
	Cache Lines			Cache Lines			Cache Lines					Clock
Transaction
			MBytes			MBytes			MBytes	Clks/	MBytes	Ratio
	Clks			Clks			Clks
			sec			sec			sec	Line	sec
64-bit Writes	10		213	18		237	26		246	4	266	5:2
64-bit Reads	16		133	24		178	32		200	4	266
32-bit Writes	18		118	34		125	50		128	8	133
32-bit Reads	24		89	40		107	56		114	8	133
64-bit Writes	10		427	18		474	26		492	4	533	3:2
64-bit Reads	19		225	27		316	37		346	4	533
32-bit Writes	18		237	34		251	50		256	8	267
32-bit Reads	28		152	44		194	60		213	8	267
64-bit Writes	10		213	18		237	26		246	4	266	3:1
64-bit Reads	16		133	24		178	32		200	4	266
32-bit Writes	18		118	34		125	50		128	8	133
32-bit Reads	24		89	40		107	56		114	8	133
64-bit Writes	10		213	18		237	26		246	4	266	2:1
64-bit Reads	18		118	26		164	34		188	4	266
32-bit Writes	18		118	34		125	50		128	8	133
32-bit Reads	26		82	42		102	58		110	8	133
64-bit Writes	10		427	18		474	30		427	5	427	1:1
64-bit Reads	23		186	34		251	46		278	5.5	388
32-bit Writes	18		237	34		251	50		256	8	267
32-bit Reads	31		138	47		182	63		203	8	267

http://www.mcg.mot.com/literature 3-9