Block Diagram
Flash Memory
The MVME240x base board contains two banks of FLASH memory. Bank B consists of two 32-pin devices which can be populated with 1MB of FLASH memory. Only 8-bit writes are supported for this bank. Bank A has four 16-bit Smart Voltage FLASH SMT devices. With the 16Mbit FLASH devices, the FLASH size is 8MB. A jumper header associated with the first set of eight FLASH devices provides a total of 128 KB of hardware- protected boot block. Only 32-bit writes are supported for this bank of FLASH. There will be a jumper to tell the Hawk chip where to fetch the reset vector. When the jumper is installed, the Hawk chip maps 0xFFF00100 to these sockets (Bank B).
The onboard monitor/debugger, PPCBug, resides in the Flash chips. PPCBug provides functionality for:
❏Booting the system
❏Initializing after a reset
❏Displaying and modifying configuration variables
❏Running self-tests and diagnostics
❏Updating firmware ROM
Under normal operation, the Flash devices are in “read-only” mode, their contents are pre-defined, and they are protected against inadvertent writes due to loss of power conditions. However, for programming purposes, programming voltage is always supplied to the devices and the Flash contents may be modified by executing the proper program command sequence. Refer to the PFLASH command in the PPCbug Debugging Package User’s Manual for further device-specific information on modifying Flash contents.
ROM/Flash Performance
The SMC provides the interface for two blocks of ROM/Flash. Access times to ROM/Flash are programmable for each block. Access times are also affected by block width. The following tables in this subsection show access times for ROM/Flash when configured for different device access times.
http://www.mcg.mot.com/literature | 3-19 |
