CHAPTER 2 NDA-24296

Page 136

Revision 1.0
PU-SW00/PU-SW00-A
Time Division Switch

Figure 2-63 Location of PU-SW00/PU-S W00-A (TSW) for IPX-UMG System

HSW01
HSW00
TSW03
TSW02
TSW01
TSW00
LANI
LANI
LANI
LANI
HSW11
HSW10
TSW13
TSW12
TSW11
TSW10
PLO 1
PLO 0
RES
CPU CPU
MMC
MISC
EMA
RES
RES RES
IOGT1
IOGT0
ISAGT ISAGT
ISAGT2 ISAGT2
MISC
I/O
BUS
MISC
I/O
BUS
ISAGT BUS
P-BUS
ISAGT BUS
P-BUS
CMP
TSW I/O BUSTSW I/O BUS
ISWM
[INT Configuration]
PCI MEM
PCI BUS PCI BUS
PCI MEM