CHAPTER 3 NDA-24296

Page 236

Revision 1.0
PH-CK17-A
Phase Lock Oscillato r

Figure 3-33 sho ws an ex ample of dist ributin g cloc k from a digi tal int erface. T his figur e assum es tha t the Di gital

Trunk POUT leads are used as the first clock distribution route. (This connection is not required for IPX-UMG

system.)

Fig ure 3-33 Cable Connection Dia gra m (4 -I MG Syste m/LN) for Receiving Clock from Digital Interface

DIU0A1
DIU0B1
DIU1A1
DIU1B1
DIU2A1
DIU2B1
DIU3A1
DIU3B1
DIU0A0
DIU0B0
DIU1A0
DIU1B0
DIU2A0
DIU2B0
DIU3A0
DIU3B0
RA
RB
TA
TB
POUT A
POUT B
PCM Cable (2P) to other node
PCM
Carrier
Equipment
DSU
CLK
Note 1:
Note 2
Note 1
PLO has a maximum of 4 inputs. DIU0xx leads are used for the 1st clock distribution routes.
DIU3xx leads are used for the 4th. The first input has the highest priority.
Note 2: The connection is required for a dual PLO system.

MDF

maximum 100
meters (330 feet)
(24AWG)
Installation Cable
LT Connector
Installation Cable
Installation Cable
EXCLK1
PLO#1
EXCLK0
PLO#0
Digital
Interface

IMG

maximum 200 meters (660 feet) (24 AWG)