NEC 2400 ipx - page 208

CHAPTER 3 NDA-24296
Page 182
Revision 1.0
PH-CK16
Phase Lock Oscillato r
The source clock of the clock subordina t e office is either the digital clock supply (DCS) or the digital interface
clock (DIU0 - DIU3). When clock source failure has occurred, the PLO chooses another clock source
automatically in the order of:
1. DCS
2. DIU0
3. DIU1
4. DIU2
5. DIU3
6. PLO changeover or the PLO internal oscillator drifting
The PLO can output the clock signals (CLK) and the frame head signals (FH) as follows:
•32.768 MHz CLK
•8 KHz FH
•5 m s ec × “n” FH