NEC 2400 ipx - page 142

CHAPTER 2 NDA-24296
Page 116
Revision 1.0
PH-SW10
Time Division Switch
Figure 2-52 shows the clock signal routing around the Phase Locked Oscillator (PL O).
Figu re 2-52 PLO Fu nc ti on Diagr am
When t he syste m ope rates as the clock source offic e of the digital network, the OSC (PA-C K14) car d is requir ed,
and th e OSC supplie s the high- precision cloc k signals (±0.3 ppm devi ation) for the bas e clock of the PLO. When
the system operates as the clock subordinate office, the TSW internal oscillator (±5 ppm deviation) c a n be the
base cl ock of the PLO. The sourc e clock of th e subordinat e office is eith er the digita l cloc k supply (DCS) or the
digital interface clock (DIU0 - DIU3). When the clock source failure has occurred, the PLO chooses another
clock source automatically in the order of:
1. DCS0
2. DCS1
3. DIU0
4. DIU1
5. DIU2
6. DIU3
7. Drifting with the TSW internal oscillator
TSW#1 (PH-SW10)
TSW#0 (PH-SW10)
TSW
TSW
PLO
PLO
OSC#1 (PA-CK14)
OSC#0 (PA-CK14)
DCS 0 DCS 1
DCS 1
DCS 0
DIU 0
DIU 1
DIU 2
DIU 3
Multiple connection on MDF