CHAPTER 3 NDA-24296

Page 234

Revision 1.0
PH-CK17-A
Phase Lock Oscillato r

Figure 3-31 shows an example of dis tributing clock from a digital interface in LN/LMG. This example assumes

that the Digital Trunk POUT leads are used as the first clock distribution route.

Figure 3-31 Cable Connection Diagram ( ISWM) fo r Receiving Clock from Digital Interface

MDF
ISW/CMG
LN/LMG
PCM
Carrier
Equipment
DSU
CLK
PCM Cable (2P) to other node
Installation Cable
Installation Cable
maximum 100
meters (330 feet)
(24AWG)
Installation Cable RA
RB
TA
TB
POUTA
POUTB
DIU0A0
DIU0B0
DIU1A0
DIU1B0
DIU2A0
DIU2B0
DIU3A0
DIU3B0
DIU0A1
DIU0B1
DIU1A1
DIU1B1
DIU2A1
DIU2B1
DIU3A1
DIU3B1
EXCLK0
PLO#0
LT Connector
Digital
Interface
EXCLK1
PLO#1
maximum 200 meters (660 feet) (24AWG)

Note 1:

Note 1
Note 2

PLO has a maximum 4 inputs. DIU0xx leads are used for the 1st clock distribution routes. DIU3xx

leads are used for the 4th. The first input has the highest priority.

Note 2: The connection is required for a dual PLO system.