The communication data on the
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| PC01 |
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| PC01 |
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| ON | 1 |
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| I / O | 2 |
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| PC00 |
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| Operation cycle | (Communication) | |
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| P C 0 1 |
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9 | Delay of input module |
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Time required for PC to detect input state (one operation cycle max.) | ||||
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Operation time of sending PC (one operation cycle)
Time to complete sending of operation result (one communication cycle max.)
Time required for receiving PC to write receive data in PC data memory (one operation cycle max.)
Operation time of receiving PC (one operation cycle) Delay of output module
Communication delay time is the total time of to above.
Remarks
The buffer memory contents of the