2.4 System Board Troubleshooting | 2 Troubleshooting Procedures |
Table 2-4 Debug port (Boot mode) error status (3/9)
D port status | Inspection items | Details |
|
|
|
(F100h) | Initialization of H/W (before DRAM | Initialization of MCHM |
| recognition) |
|
| Initialization of ICH4M.D31.Func0 | |
|
| |
|
|
|
|
| Initialization of ICH4M.D31.Func1 |
|
|
|
|
| Initialization of USB.Func0,1,2,7 |
|
|
|
|
| Initialization of ICH4M.D31.Func3 |
|
|
|
|
| Initialization of ICH4M.D31.Func5 |
|
|
|
|
| Initialization of TI |
|
|
|
| Initialization of PIT channel 1 | (Setting the refresh interval to “30? s”) |
|
|
|
F101h | Checking DRAM type and size (at | When unsupported memory connected, |
| beeps and halts. | |
| cold boot) | |
| When DRAM size = 0, halts. | |
|
| |
|
|
|
| Testing the stack area of | When it can not be used, halts. |
|
|
|
F102h | Configuring cache memory |
|
|
|
|
| Permission of L1/L2 cache |
|
| memory |
|
|
|
|
| Checking the access of a CMOS | When error detected, halts |
| (Only in Cold Boot) | |
|
| |
|
|
|
| Examining the battery level of |
|
| CMOS |
|
|
|
|
| Checksum check of CMOS |
|
|
|
|
| Initializing data in CMOS (1) |
|
|
|
|
| Setting up IRT status | (Setting of boot status and IRT busy flag, |
| The rest bits are 0) | |
|
| |
|
|
|
| Storing the size of DRAM |
|
|
|
|
F103h | Branch of resuming( only in Cold | When a CMOS error is detected, it does |
| Boot) | not resume. |
|
|
|
|
| If “resume status code” is not set, no |
|
| resume occurs. |
|
|
|
QOSMIO F10 Maintenance Manual |
