Intel 317698-001 manual Polarity Inversion, Lane Reversal

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82575 Ethernet Controller Design Guide

If Maximum Link Width = x2, then the 82575 Ethernet Controller negotiates to either x2 or x1

If Maximum Link Width = x1, then the 82575 Ethernet Controller only negotiates to x1

2.3.2Polarity Inversion

If polarity inversion is detected the Receiver must invert the received data.

During the training sequence, the Receiver looks at Symbols 6-15 of TS1 and TS2 as the indicator of lane polarity inversion (D+ and D- are swapped). If lane polarity inversion occurs, the TS1 Symbols 6-15 received will be D21.5 as opposed to the expected D10.2. Similarly, if lane polarity inversion occurs, Symbols 6-15 of the TS2 ordered set will be D26.5 as opposed to the expected D5.2. This provides the clear indication of lane polarity inversion.

2.3.3Lane Reversal

The following lane reversal modes are supported (see Figure below):

Lane configuration of x4, x2, and x1

Lane reversal in x4 and in x2

Degraded mode (downshift) from x4 to x2 to x1 and from x2 to x1, with one restriction - if lane reversal is executed in x4, then downshift is only to x1 and not to x2.

These restrictions require that a x2 interface to the 82575 Ethernet Controller must connect to lanes 0 &1 on the 82575 Ethernet Controller. The PCI Express Card Electromechanical specification does not allow routing a x2 link to a wider connector. Therefore, the system designer is not allowed to connect a x2 link to lanes 2 and 3 of a PCI Express connector. It is also recommended that, when using x2 mode on a network interface card, the 82575 Ethernet Controller be connected to lanes 0 & 1 of the card.

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Link Width Configuration Other PCI Express SignalsPhysical Layer Features PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Clock Source Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Magnetics for 1000 BASE-TThird-Party Magnetics Manufacturers Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSerial Eeprom Symbol Ball # Name and functionFunction Default Control options General RegionsSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Eeupdate FlashFlash Write Control Flash Erase ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0a82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Smartspeed Low-Power Link UpUsing SmartSpeed Flow ControlPolarity Correction Link Energy Detect25.6 Reg Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Quartz Crystal Frequency Control Device Design ConsiderationsFrequency Control Component Types Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorCrystal Selection Parameters Vibrational ModeTemperature Stability and Environmental Requirements Nominal FrequencyCalibration Mode Load CapacitanceDrive Level Shunt CapacitanceEquivalent Series Resistance AgingReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Routing 1.8 V to the Magnetics Center Tap Signal IsolationSignal Detect Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsThermal Design Considerations Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Symbol Design and Layout ChecklistsReference Schematics Thermal Management

317698-001 specifications

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