Intel 317698-001 manual L0s D0u D0a, 4.2 82575 Ethernet Controller Power Management

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82575 Ethernet Controller Design Guide

Internal_Power_On

_Reset assertion

L3

Dr

 

PERST# de-

 

 

assertion

L0

 

 

 

 

 

 

L2

 

PERST#

 

 

 

assertion

 

 

 

PERST#

 

 

Enable

 

 

master Access

 

assertion

 

 

 

 

 

 

 

Write 00

PERST#

 

 

 

to Power State

 

 

 

assertion

 

 

 

 

 

 

 

L1

 

L0

 

 

Write 11

 

 

to Power State

 

D3

L0s

D0u

L1

L0s

D0a

L1

Figure 8. PCIe Power Management Flow/State Diagram

3.4.4.282575 Ethernet Controller Power Management

If DisableD3Cold=0, the 82575 uses the AUX_PWR indication that auxiliary power is available to the controller, and therefore advertises D3cold Wake Up support. The amount of power required for the function (which includes the entire network interface card) is advertised in the Power Management Data Register, which is loaded from the

EEPROM.

If D3cold is supported, the PME_En and PME_Status bits of the Power Management Control/Status Register (PMCSR), as well as their shadow bits in the Wake Up Control Register (WUC) will be reset only by the power up reset (detection of power rising).

The only effect of setting AUX_PWR to 1 is advertising D3cold Wake Up support and changing the reset function of PME_En and PME_Status. AUX_PWR is a strapping option in the 82575.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents PCI Express Port Connection to the Device Other PCI Express SignalsPhysical Layer Features Link Width ConfigurationLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank Magnetics for 1000 BASE-T Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Clock SourceManufacturer Part Number Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Third-Party Magnetics ManufacturersPCI Function # Select PCI/LAN Function IndexGeneral Regions Symbol Ball # Name and functionFunction Default Control options Serial EepromEeprom Map Information SPI EEPROMs for 82575 Ethernet Controller ControllerManufacturer Size Manufacturers Part Number Flash EeupdateFlash Erase Control Flash Write ControlSMBus and NC-SI Flash Device InformationManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY 2 82575 Ethernet Controller Device Power Supply Filtering Using Regulators With Enable PinsPower Rail 7uF or 1uF 10uF PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power ManagementAuto Cross-over for MDI and MDI-X resolution 82575 Ethernet Controller Device Test CapabilityPHY Functionality Flow Control Low-Power Link UpUsing SmartSpeed SmartspeedLink Energy Detect Polarity Correction25.6 Reg Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Fixed Crystal Oscillator Frequency Control Device Design ConsiderationsFrequency Control Component Types Quartz CrystalCeramic Resonator Programmable Crystal OscillatorsNominal Frequency Vibrational ModeTemperature Stability and Environmental Requirements Crystal Selection ParametersLoad Capacitance Calibration ModeAging Shunt CapacitanceEquivalent Series Resistance Drive LevelTemperature Changes Reference Crystal SelectionCircuit Board This page is intentionally left blank Oscillator Solution Specifications Symbol Parameter Units Min Typical MaxOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Guidelines for Component Placement Ethernet Component Layout GuidelinesLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsSignal Trace Geometry for 1000 BASE-T Designs Signal Termination and CouplingTrace Length and Symmetry for 1000 BASE-T Designs Impedance Discontinuities Signal IsolationSignal Detect Routing 1.8 V to the Magnetics Center TapTraces for Decoupling Capacitors Power and Ground PlanesConformance Tests for 10/100/1000 Mbps Designs Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Thermal Design ConsiderationsEthernet Controller Design Guide Thermal Management Design and Layout ChecklistsReference Schematics Symbol

317698-001 specifications

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