Intel 317698-001 manual Copper/Fiber Switch, SerDes-Detect Mode PHY is active

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82575 Ethernet Controller Design Guide

is complete, the driver must read the PHY registers to determine the resolved flow control behavior of the link and reflect these in the MAC register settings (CTRL.TFCE and CTRL.RFCE).

Note: Once PHY Auto-negotiation is complete, the PHY will assert a link indication (LINK) to the MAC. Software must have set the "Set Link Up" bit in the Device Control Register (CTRL.SLU) before the MAC recognizes the LINK indication from the PHY and can consider the link to be up.

3.7Copper/Fiber Switch

The 82575 Ethernet Controller provides significant amount of flexibility in pairing a LAN device with a particular type of media (copper or fiber-optic) as well as the specific transceiver/interface used to communicate with the media. Each MAC, representing a distinct LAN device, can be coupled with an internal copper PHY (the default) or SERDES interface independently. The link configuration specified for each LAN device may be specified in the LINK_MODE field of the Extended Device Control Register (CTRL_EXT) and initialized from the EEPROM Initialization Control Word 3 associated with each LAN device.

In some applications, the software may need to be aware of the presence of a link on the connection not currently active. In order to supply such an indication, any of the the 82575 Ethernet Controller ports may set the AUTOSENSE_EN bit in the CONNSW register (address 0x00034) in order to enable sensing of the non-active connection activity. When in SerDes detect mode, the software should define which indication is used to detect the energy change in SerDes/SGMII mode. It can be either the external signal detect pin or the internal signal detect. This is done using the CONNSW.ENRGSRC bit.

The software can then enable the OMED interrupt in ICR in order to get an indication of any detection of energy in the non active connection.

The following procedure should be followed in order to enable the auto-sense mode:

SerDes-Detect Mode (PHY is active)

•Set CONNSW.ENRGSRC to determine the sources for the signal detect indication (1- external SIG_DET, 0- internal SerDes electrical idle). The default of this bit is set by EEPROM.

•Set CONNSW.AUTOSENSE_EN.

•When signal is detected on the SerDes link, the 82575 Ethernet Controller will set the interrupt bit OMED in ICR and, if enabled, issue an interrupt. The CONNSW.AUTOSENSE_EN will be cleared unless CONNSW.ASCLR_DIS is set. In such a case, the host driver is responsible for the clearing of the AUTOSENSE_EN bit.

PHY-Detect Mode

•Set CONNSW.AUTOSENSE_CONF = 1.

•Reset the PHY by assertion and de-assertion of CTRL.PHY_RST.

•Wait until EEMNGCTL.CFG_DONE is set.

•Enter the PHY to Link-Disconnect mode by setting why-reg25.5 via MDIC register.

•Set CONNSW.AUTOSENSE_EN = 1 and clear CONNSW.AUTOSENSE_CONF.

•When signal is detected on the PHY link, the hardware will set the interrupt bit OMED in ICR and, if enabled, issue an interrupt.

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Other PCI Express Signals Physical Layer FeaturesLink Width Configuration PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Ethernet Component Design Guidelines General Design Considerations for Ethernet ControllersClock Source Magnetics for 1000 BASE-TDesigning with the 82575/EB/ES Gigabit Ethernet Controller Modules for 1000 BASE-T EthernetThird-Party Magnetics Manufacturers Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSymbol Ball # Name and function Function Default Control optionsSerial Eeprom General RegionsManufacturer Size Manufacturers Part Number Eeprom Map InformationSPI EEPROMs for 82575 Ethernet Controller Controller Eeupdate FlashFlash Write Control Flash Erase ControlManufacturer Device SMBus and NC-SIFlash Device Information Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY Power Rail 7uF or 1uF 10uF 2 82575 Ethernet Controller Device Power Supply FilteringUsing Regulators With Enable Pins Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0aPHY Functionality Auto Cross-over for MDI and MDI-X resolution82575 Ethernet Controller Device Test Capability Low-Power Link Up Using SmartSpeedSmartspeed Flow Control25.6 Reg Link Energy DetectPolarity Correction Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Frequency Control Device Design Considerations Frequency Control Component TypesQuartz Crystal Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorVibrational Mode Temperature Stability and Environmental RequirementsCrystal Selection Parameters Nominal FrequencyCalibration Mode Load CapacitanceShunt Capacitance Equivalent Series ResistanceDrive Level AgingCircuit Board Temperature ChangesReference Crystal Selection This page is intentionally left blank Oscillator Support Oscillator SolutionSpecifications Symbol Parameter Units Min Typical Max VGG=0.6V Rpar =100MΩ Cpar =20pF Layout Considerations for 82575 Ethernet Controllers Guidelines for Component PlacementEthernet Component Layout Guidelines LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingTrace Length and Symmetry for 1000 BASE-T Designs Signal Trace Geometry for 1000 BASE-T DesignsSignal Termination and Coupling Signal Isolation Signal DetectRouting 1.8 V to the Magnetics Center Tap Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsPhysical Layer Conformance Testing Troubleshooting Common Physical Layout IssuesThermal Design Considerations Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Design and Layout Checklists Reference SchematicsSymbol Thermal Management

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