Intel 317698-001 manual Shunt Capacitance, Equivalent Series Resistance, Drive Level, Aging

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82575 Ethernet Controller Design Guide

An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load capacitance is 16 pF with an estimated stray capacitance of about 5 pF.

Individual stray capacitance components can be estimated and added. For example, surface mount pads for the load capacitors add approximately 2.5 pF in parallel to each capacitor. This technique is especially useful if Y1, C1 and C2 must be placed farther than approximately one-half (0.5) inch from the device. It is worth noting that thin circuit boards generally have higher stray capacitance than thick circuit boards. Consult the PCIe Design Guide for more information.

The oscillator frequency should be measured with a precision frequency counter where possible. The load specification or values of C1 and C2 should be fine tuned for the design. As the actual capacitance load increases, the oscillator frequency decreases.

Note: C1 and C2 may vary by as much as 5% (approximately 1 pF) from their nominal values.

5.7Shunt Capacitance

The shunt capacitance parameter is relatively unimportant compared to load capacitance. Shunt capacitance represents the effect of the crystal’s mechanical holder and contacts. The shunt capacitance should equal a maximum of 7 pF.

5.8Equivalent Series Resistance

Equivalent Series Resistance (ESR) is the real component of the crystal’s impedance at the calibration frequency, which the inverting amplifier’s loop gain must overcome. ESR varies inversely with frequency for a given crystal family. The lower the ESR, the faster the crystal starts up. Use crystals with an ESR value of 50 Ω or better.

5.9Drive Level

Drive level refers to power dissipation in use. The allowable drive level for a Surface Mounted Technology (SMT) crystal is less than its through-hole counterpart, because surface mount crystals are typically made from narrow, rectangular AT strips, rather than circular AT quartz blanks.

Some crystal data sheets list crystals with a maximum drive level of 1 mW. However, Intel Ethernet controllers drive crystals to a level less than the suggested 0.5 mW value. This parameter does not have much value for on-chip oscillator use.

5.10Aging

Aging is a permanent change in frequency (and resistance) occurring over time. This parameter is most important in its first year because new crystals age faster than old crystals. Use crystals with a maximum of ±5 ppm per year aging.

5.11Reference Crystal

The normal tolerances of the discrete crystal components can contribute to small frequency offsets with respect to the target center frequency. To minimize the risk of tolerance-caused frequency offsets causing a small percentage of production line units to be outside of the acceptable frequency range, it is important to account for those shifts while empirically determining the proper values for the discrete loading capacitors, C1 and C2.

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Other PCI Express Signals Physical Layer FeaturesLink Width Configuration PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Ethernet Component Design Guidelines General Design Considerations for Ethernet ControllersClock Source Magnetics for 1000 BASE-TDesigning with the 82575/EB/ES Gigabit Ethernet Controller Modules for 1000 BASE-T EthernetThird-Party Magnetics Manufacturers Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSymbol Ball # Name and function Function Default Control optionsSerial Eeprom General RegionsSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Eeupdate FlashFlash Write Control Flash Erase ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0a82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Low-Power Link Up Using SmartSpeedSmartspeed Flow ControlPolarity Correction Link Energy Detect25.6 Reg Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Frequency Control Device Design Considerations Frequency Control Component TypesQuartz Crystal Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorVibrational Mode Temperature Stability and Environmental RequirementsCrystal Selection Parameters Nominal FrequencyCalibration Mode Load CapacitanceShunt Capacitance Equivalent Series ResistanceDrive Level AgingReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Signal Isolation Signal DetectRouting 1.8 V to the Magnetics Center Tap Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsPhysical Layer Conformance Testing Troubleshooting Common Physical Layout IssuesThermal Design Considerations Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Design and Layout Checklists Reference SchematicsSymbol Thermal Management

317698-001 specifications

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