Intel 317698-001 manual Designing with the 82575/EB/ES Gigabit Ethernet Controller

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82575 Ethernet Controller Design Guide

consistent from sample to sample and that measurements meet the published specifications.

3.Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. Vary temperature and voltage while performing system level tests.

3.1.2.2Modules for 1000 BASE-T Ethernet

Magnetics modules for 1000 BASE-T Ethernet are similar to those designed solely for 10/100 Mbps, except that there are four differential signal pairs instead of two. Use the following guidelines to verify specific electrical parameters:

1.Verify that the rated return loss is 19 dB or greater from 2 MHz through 40 MHz for 100/1000 BASE-TX.

2.Verify that the rated return loss is 12 dB or greater at 80 MHz for 100 BASE-TX (the specification requires greater than or equal to 10 dB).

3.Verify that the rated return loss is 10 dB or greater at 100 MHz for 1000 BASE-TX (the specification requires greater than or equal to 8 dB).

4.Verify that the insertion loss is less than 1.0 dB at 100 kHz through 80 MHz for 100 BASE-TX.

5.Verify that the insertion loss is less than 1.4 dB at 100 kHz through 100 MHz for 1000 BASE-T.

6.Verify at least 30 dB of crosstalk isolation between adjacent channels (through 150 MHz).

7.Verify high voltage isolation to 15000 Vrms. (Does not apply to discrete magnetics.)

8.Transmitter OCL should be greater than or equal to 350 μH with 8 mA DC bias.

3.1.2.3Third-Party Magnetics Manufacturers

The following magnetics modules have been used successfully in previous designs..

Manufacturer

Part Number

 

 

Pulse

H5007

 

 

Bel (discrete)

Bel 0344FLA

 

 

3.1.2.4Layout Guidelines for Use with Integrated and Discrete Magnetics

Layout requirements are slightly different when using discrete magnetics. These include:

•Ground cut for HV installation (not required for integrated magnetics)

•A maximum of two (2) vias

•Turns less than 45°

•Discrete terminators

3.2Designing with the 82575/EB/ES Gigabit Ethernet Controller

This section provides design guidelines specific to the 82575/EB/ES controller.

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Link Width Configuration Other PCI Express SignalsPhysical Layer Features PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Clock Source Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Magnetics for 1000 BASE-TThird-Party Magnetics Manufacturers Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSerial Eeprom Symbol Ball # Name and functionFunction Default Control options General RegionsManufacturer Size Manufacturers Part Number Eeprom Map InformationSPI EEPROMs for 82575 Ethernet Controller Controller Eeupdate FlashFlash Write Control Flash Erase ControlManufacturer Device SMBus and NC-SIFlash Device Information Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY Power Rail 7uF or 1uF 10uF 2 82575 Ethernet Controller Device Power Supply FilteringUsing Regulators With Enable Pins Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0aPHY Functionality Auto Cross-over for MDI and MDI-X resolution82575 Ethernet Controller Device Test Capability Smartspeed Low-Power Link UpUsing SmartSpeed Flow Control25.6 Reg Link Energy DetectPolarity Correction Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Quartz Crystal Frequency Control Device Design ConsiderationsFrequency Control Component Types Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorCrystal Selection Parameters Vibrational ModeTemperature Stability and Environmental Requirements Nominal FrequencyCalibration Mode Load CapacitanceDrive Level Shunt CapacitanceEquivalent Series Resistance AgingCircuit Board Temperature ChangesReference Crystal Selection This page is intentionally left blank Oscillator Support Oscillator SolutionSpecifications Symbol Parameter Units Min Typical Max VGG=0.6V Rpar =100MΩ Cpar =20pF Layout Considerations for 82575 Ethernet Controllers Guidelines for Component PlacementEthernet Component Layout Guidelines LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingTrace Length and Symmetry for 1000 BASE-T Designs Signal Trace Geometry for 1000 BASE-T DesignsSignal Termination and Coupling Routing 1.8 V to the Magnetics Center Tap Signal IsolationSignal Detect Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsThermal Design Considerations Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Symbol Design and Layout ChecklistsReference Schematics Thermal Management

317698-001 specifications

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