Intel 317698-001 manual Oscillator Support, Oscillator Solution

Page 43

82575 Ethernet Controller Design Guide

6.0Oscillator Support

The 82575 clock input circuit is optimized for use with an external crystal. However, an oscillator can also be used in place of the crystal with the proper design considerations:

•The clock oscillator has an internal voltage regulator of 1.2 V to isolate it from the external noise of other circuits to minimize jitter. If an external clock is used, this imposes a maximum input clock amplitude of 1.2 V.

•The input capacitance introduced by the 82575 (approximately 20 pF) is greater than the capacitance specified by a typical oscillator (approximately 15 pF).

•The input clock jitter from the oscillator can impact the 82575 clock and its performance.

Table 8.

82575 Clock Oscillator Specifications

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Specifications

 

 

 

Symbol

Parameter

 

 

 

 

 

Units

 

 

 

 

 

 

 

 

 

Min

 

Typical

 

Max

 

 

 

 

 

 

 

 

 

 

 

f0

Frequency (@25°C)

-

 

25

 

-

MHz

 

 

 

 

 

 

 

 

 

 

Vp-p

External Oscillator Supply Swing

3.0

 

3.3

 

3.6

V

 

 

 

 

 

 

 

 

 

 

Vscp-p

XTAL1 Swing

1.1

 

1.2

 

1.3

V

 

 

 

 

 

 

 

 

 

 

Df/fo

Frequency Tolerance (@ -20 to +70 °C)

-

 

±50

 

 

ppm

 

Topr

Operating Temperature

-

 

-20 to

 

 

°C

 

 

+70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Δf/fo

Aging

-

 

±5

 

 

ppm/year

 

Ccoupling

Coupling Capacitor

8

 

10

 

12

pF

 

 

 

 

 

 

 

 

 

Note: The power consumption of additional circuitry equals about 1.5 mW.

The following table lists oscillators that have been used successfully in past designs (please note that no particular product is recommended):

Table 9. Oscillator Manufacturers and Part Numbers

Manufacturer

Part No.

 

 

RALTRON

CO4305-25.000-TR

 

 

CITIZEN AMERICA CORP

CSX750FBB25.000MTR

 

 

6.1Oscillator Solution

This solution involves capacitor C1, which forms a capacitor divider with Cstray of about 20 pF. This attenuates the input clock amplitude and adjusts the clock oscillator load capacitance.

Vin = VDD * (C1/(C1 + Cstray))

Vin = 3.3 * (C1/(C1 + Cstray))

This enables load clock oscillators of 15 pF to be used. If the value of Cstray is unknown, C1 should be adjusted by tuning the input clock amplitude to approximately 1 Vptp. If Cstray equals 20 pF, then C1 is 10 pF ±10%.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents PCI Express Port Connection to the Device Other PCI Express SignalsPhysical Layer Features Link Width ConfigurationLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank Magnetics for 1000 BASE-T Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Clock SourceManufacturer Part Number Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Third-Party Magnetics ManufacturersPCI Function # Select PCI/LAN Function IndexGeneral Regions Symbol Ball # Name and functionFunction Default Control options Serial EepromSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Flash EeupdateFlash Erase Control Flash Write ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power Management82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Flow Control Low-Power Link UpUsing SmartSpeed SmartspeedPolarity Correction Link Energy Detect25.6 Reg Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Fixed Crystal Oscillator Frequency Control Device Design ConsiderationsFrequency Control Component Types Quartz CrystalCeramic Resonator Programmable Crystal OscillatorsNominal Frequency Vibrational ModeTemperature Stability and Environmental Requirements Crystal Selection ParametersLoad Capacitance Calibration ModeAging Shunt CapacitanceEquivalent Series Resistance Drive LevelReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Impedance Discontinuities Signal IsolationSignal Detect Routing 1.8 V to the Magnetics Center TapTraces for Decoupling Capacitors Power and Ground PlanesConformance Tests for 10/100/1000 Mbps Designs Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Thermal Design ConsiderationsEthernet Controller Design Guide Thermal Management Design and Layout ChecklistsReference Schematics Symbol

317698-001 specifications

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