Intel 317698-001 manual Software-Definable Pins SDPs, Bios handling of Device Disable

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82575 Ethernet Controller Design Guide

Note that if the device is configured to provide a 50MHz NC-SI clock (via the NC-SI Output Clock EEPROM bit), then the NC-SI clock must be provided in Device Disable mode as well the device should not be disabled.

Device Disable is initiated by asserting the asynchronous DEV_OFF_N pin. The

DEV_OFF_N pin has an internal pull-up resistor, so that it can be left not connected to enable device operation.

The EEPROM’s "Device Disable Power Down En" bit enables device disable mode (hardware default is that the mode is disabled).

While in device disable mode, the PCI Express link is in L3 state. The PHY is in power down mode. Output buffers are tri-stated.

Assertion or deassertion of PCI Express PE_RST_N does not have any effect while the device is in device disable mode (that is, the device stays in the respective mode as long as DEV_OFF_N is asserted). However, the device may momentarily exit the device disable mode from the time PCI Express PE_RST_N is de-asserted again and until the EEPROM is read.

During power-up, the DEV_OFF_N pin is ignored until the EEPROM is read. From that point, the device may enter Device Disable if DEV_OFF_N is asserted.

Note: The DEV_OFF_N pin should maintain its state during system reset and system sleep states. It should also insure the proper default value on system power-up. For example, one could use a GPIO pin that defaults to '1' (enable) and is on system suspend power (i.e., it maintains state in S0-S5 ACPI states).

3.8.1BIOS handling of Device Disable

Assume that in the following power up sequence the DEV_OFF_N signal is driven high (or it is already disabled)

1.The PCIe is established following the GIO_PWR_GOOD

2.BIOS recognizes that the whole Device should be disabled

3.The BIOS drive the DEV_OFF_N signal to the low level.

4.As a result, the device samples the DEV_OFF_N signals and enters either the device disable mode.

5.The BIOS could put the Link in the Electrical IDLE state (at the other end of the PCI Express link) by clearing the LINK Disable bit in the Link Control Register.

6.BIOS may start with the Device enumeration procedure (the whole Device functions are invisible)

7.Proceed with Nominal operation

8.Re-enable could be done by driving hi the DEV_OFF_N signal, followed later by bus enumeration.

3.9Software-Definable Pins (SDPs)

The 82575 has four software-defined pins (SDP) per port that can be used for miscellaneous hardware or software-controllable purposes. These pins and their function are bound to a specific LAN device (eight SDPs may not be associated with a single LAN device, for example). These pins can each be individually configured to act as either input or output pins. The default direction of each of the four pins is configurable via EEPROM, as well as the default value of any pins configured as outputs.

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Link Width Configuration Other PCI Express SignalsPhysical Layer Features PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Clock Source Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Magnetics for 1000 BASE-TThird-Party Magnetics Manufacturers Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSerial Eeprom Symbol Ball # Name and functionFunction Default Control options General RegionsSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Eeupdate FlashFlash Write Control Flash Erase ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0a82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Smartspeed Low-Power Link UpUsing SmartSpeed Flow ControlPolarity Correction Link Energy Detect25.6 Reg Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Quartz Crystal Frequency Control Device Design ConsiderationsFrequency Control Component Types Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorCrystal Selection Parameters Vibrational ModeTemperature Stability and Environmental Requirements Nominal FrequencyCalibration Mode Load CapacitanceDrive Level Shunt CapacitanceEquivalent Series Resistance AgingReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Routing 1.8 V to the Magnetics Center Tap Signal IsolationSignal Detect Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsThermal Design Considerations Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Symbol Design and Layout ChecklistsReference Schematics Thermal Management

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