Intel 317698-001 manual Device Disable, Internal PHY-to-SerDes Transition

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82575 Ethernet Controller Design Guide

•The 82575 will put the PHY in power down unless CONNSW.ASCLR_DIS is set. In such a case the host driver is responsible for the clearing of the AUTOSENSE_EN bit

According to the result of the interrupt, the software can then decide to switch to the other core.

The following procedures need to be followed to actually switch between the two modes:

Internal PHY-to-SerDes Transition

•Disable Receiver by clearing RCTL.RXEN

•Disable Transmitter by clearing TCTL.EN

•Verify the device has stopped processing outstanding cycles and is idle.

•Modify LINK mode to SER/DES or SGMII by setting CTRL_EXT.LINK_MODE to 10b or 11b respectively.

•Enable/Disable flow control values within the MAC.

•Set up Tx and Rx queues and enable Tx and Rx processes.

SerDes-to-Internal PHY Transition

•Disable Receiver by clearing RCTL.RXEN

•Disable Transmitter by clearing TCTL.EN

•Verify the 82575 has stopped processing outstanding cycles and is idle.

•Modify LINK mode to PHY mode by setting CTRL_EXT.LINK_MODE to 00b.

•Set Link Up indication by setting CTRL.SLU

•Reset the PHY.by setting CTRL.PHY_RST, waiting 10 ms and clearing CTRL.PHY_RST.

•Set up PHY with desired auto-negotiation parameters

•Set up Tx and Rx queues and enable Tx and Rx processes.

The device's link mode is controlled by the Extended Device Control register --

CTRL_EXT (0x00018) bits 23:22. The default value for the LINK_MODE setting is directly mapped from the EEPROM's initialization Control Word 3 (bits 1:0). Software can modify the LINK_MODE indication by writing the corresponding value into this register.

Note: Before dynamically cycling a mode, ensure via the software device driver that the current mode of operation is not in the process of transmitting or receiving data. This is achieved by disabling the transmitter and receiver, waiting until the device is in an idle state, and then beginning the process for changing the link mode.

Note: The mode switch in this method, is only valid until the next hardware reset of the chip. After hardware reset the link mode is restored to the default set by the EEPROM. To get a permanent change of the link mode, the default in the EEPROM should be changed.

3.8Device Disable

For a LOM design, it may be desirable for the system to provide BIOS-setup capability for selectively enabling or disabling LOM devices. This may allow the end-user more control over system resource-management, avoid conflicts with add-in NIC solutions, etc. the 82575 Ethernet Controller provides support for selectively enabling or disabling it.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents Physical Layer Features Other PCI Express SignalsLink Width Configuration PCI Express Port Connection to the DeviceLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank General Design Considerations for Ethernet Controllers Ethernet Component Design GuidelinesClock Source Magnetics for 1000 BASE-TModules for 1000 BASE-T Ethernet Designing with the 82575/EB/ES Gigabit Ethernet ControllerThird-Party Magnetics Manufacturers Manufacturer Part NumberPCI Function # Select PCI/LAN Function IndexFunction Default Control options Symbol Ball # Name and functionSerial Eeprom General RegionsEeprom Map Information SPI EEPROMs for 82575 Ethernet Controller ControllerManufacturer Size Manufacturers Part Number Flash EeupdateFlash Erase Control Flash Write ControlSMBus and NC-SI Flash Device InformationManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY 2 82575 Ethernet Controller Device Power Supply Filtering Using Regulators With Enable PinsPower Rail 7uF or 1uF 10uF PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power ManagementAuto Cross-over for MDI and MDI-X resolution 82575 Ethernet Controller Device Test CapabilityPHY Functionality Using SmartSpeed Low-Power Link UpSmartspeed Flow ControlLink Energy Detect Polarity Correction25.6 Reg Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Frequency Control Component Types Frequency Control Device Design ConsiderationsQuartz Crystal Fixed Crystal OscillatorCeramic Resonator Programmable Crystal OscillatorsTemperature Stability and Environmental Requirements Vibrational ModeCrystal Selection Parameters Nominal FrequencyLoad Capacitance Calibration ModeEquivalent Series Resistance Shunt CapacitanceDrive Level AgingTemperature Changes Reference Crystal SelectionCircuit Board This page is intentionally left blank Oscillator Solution Specifications Symbol Parameter Units Min Typical MaxOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Guidelines for Component Placement Ethernet Component Layout GuidelinesLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsSignal Trace Geometry for 1000 BASE-T Designs Signal Termination and CouplingTrace Length and Symmetry for 1000 BASE-T Designs Signal Detect Signal IsolationRouting 1.8 V to the Magnetics Center Tap Impedance DiscontinuitiesTraces for Decoupling Capacitors Power and Ground PlanesTroubleshooting Common Physical Layout Issues Physical Layer Conformance TestingThermal Design Considerations Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Reference Schematics Design and Layout ChecklistsSymbol Thermal Management

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