Intel 317698-001 manual Introduction, Scope

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82575 Ethernet Controller Design Guide

1.0Introduction

The Intel® 82575 Ethernet Controller is a single, compact component that offers two fully-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. This device uses the PCI Express* (PCIe) architecture (Rev. 1.1RD). The 82575 enables two-port implementation in a relatively small area and can be used for server and workstation network designs with critical space constraints.

The 82575 provides:

•a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab).

•a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. Information concerning SERDES can be found in the 82575 Ethernet Controller SERDES Application Note.

•SGMII for SFP/external PHY

•management of MAC and PHY Ethernet layer functions

•management of PCI Express packet traffic across its transaction, link, and physical/ logical layers.

•I/O Acceleration Technologies (I/OAT2). to accelerate the data transactions by hardware means optimizing the TCP flow and reducing the load on the CPU.

In addition, the 82575’s on-board System Management Bus (SMB) ports enable network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. The SMB ports enable industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2.0, to be implemented using the 82575. In addition, on-chip ASF 2.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82575 Ethernet Controller contains a dedicated microcontroller for manageability with with NC-SI and DMTF support.

The 82575 with PCIe architecture is designed for high-performance and low-host- memory access latency. The device connects directly to a system Memory Control Hub (MCH) or I/O Controller Hub (ICH) using one, two, or four PCI Express lanes.

Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipelined logic architecture optimized for ethernet and independent transmit and receive queues, the 82575 efficiently handles packets with minimum latency. The 82575 includes advanced interrupt handling features. It uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 48 KByte on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation.

The 82575 is packaged in 25mm x 25mm, 576-ball grid array.

1.1Scope

This application note contains Ethernet design guidelines applicable to LOM designs based on PCI Express-supported chipsets.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents PCI Express Port Connection to the Device Other PCI Express SignalsPhysical Layer Features Link Width ConfigurationLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank Magnetics for 1000 BASE-T Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Clock SourceManufacturer Part Number Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Third-Party Magnetics ManufacturersPCI Function # Select PCI/LAN Function IndexGeneral Regions Symbol Ball # Name and functionFunction Default Control options Serial EepromSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Flash EeupdateFlash Erase Control Flash Write ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power Management82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Flow Control Low-Power Link UpUsing SmartSpeed SmartspeedPolarity Correction Link Energy Detect25.6 Reg Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Fixed Crystal Oscillator Frequency Control Device Design ConsiderationsFrequency Control Component Types Quartz CrystalCeramic Resonator Programmable Crystal OscillatorsNominal Frequency Vibrational ModeTemperature Stability and Environmental Requirements Crystal Selection ParametersLoad Capacitance Calibration ModeAging Shunt CapacitanceEquivalent Series Resistance Drive LevelReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Impedance Discontinuities Signal IsolationSignal Detect Routing 1.8 V to the Magnetics Center TapTraces for Decoupling Capacitors Power and Ground PlanesConformance Tests for 10/100/1000 Mbps Designs Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Thermal Design ConsiderationsEthernet Controller Design Guide Thermal Management Design and Layout ChecklistsReference Schematics Symbol

317698-001 specifications

The Intel 317698-001 is a prominent and highly regarded component in the realm of computer hardware. This product is part of Intel's extensive portfolio, designed primarily for enhancing computing performance, efficiency, and reliability. It is typically associated with server motherboards and is known for its robust architecture, making it ideal for enterprise-level applications.

One of the standout features of the Intel 317698-001 is its compatibility with multiple Intel processors, which provides flexibility for users looking to upgrade or configure their systems. This compatibility ensures that enterprises can choose from a range of processors according to their specific workload requirements, allowing for tailored performance enhancements.

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In terms of connectivity, the Intel 317698-001 features multiple PCIe lanes, supporting various expansion cards for enhanced functionality. This includes the integration of NVMe drives for faster storage solutions, which is essential for modern applications that demand quick data access and retrieval.

Security is also a priority with the Intel 317698-001, which incorporates hardware-based security features to protect data integrity and prevent unauthorized access. These features include Intel Trusted Execution Technology, which creates a secure environment for executing sensitive code.

Overall, the Intel 317698-001 stands out with its combination of performance, versatility, and security. It is an ideal choice for businesses looking to enhance their computing capabilities while ensuring system reliability and security in an increasingly data-driven world. With its robust technological foundation, it continues to play a critical role in modern computing environments.
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