Intel 317698-001 manual PCIe Power Management

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82575 Ethernet Controller Design Guide

logic input to the 82575 Ethernet Controller that denotes auxiliary power is available. If AUX_PWR is asserted, the 82575 Ethernet Controller device will advertise that it supports wake up from a D3cold state.

The 82575 Ethernet Controller device supports both Advanced Power Management (APM) wakeup and Advanced Configuration and Power Interface (ACPI) wakeup. APM wakeup has also been known in the past as “Wake on LAN” and as “Magic Packet Wake- up”.

Wakeup uses the PE_WAKEn signal to wake the system up. PE_WAKEn is an active low signal typically connected to a GPIO port on the chipset that goes active in response to receiving a “Magic Packet”, a network wakeup packet, or link status change indication. PE_WAKEn remains asserted until PME status is cleared in the 82575 Power Management Control/Status Register.

3.4.4Power Management

3.4.4.1PCIe Power Management

The 82575 supports D0 and D3 power states defined in the PCI Power Management and PCI Express Specifications. D0 is divided into two sub-states: D0u (D0 Un-initialized), and D0a (D0 active). In addition, the 82575 supports a Dr state that is entered when PE_RST_N is asserted (including the D3cold state).

The diagrams below show the power states and transitions between them.

Internal_Power_On

Hot (in-band)

_Reset assertion

Reset

PERST# de-

assertion &

EEPROM read

done

Dr

PERST# assertion

D0u

PERST# assertion

Write 11

to Power State

Write 00

to Power State

PERST# assertion

Enable

master or slave

Access

D3

Write 11

D0a

to Power State

Figure 7. Power Management State Diagram

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Link Width Configuration Other PCI Express SignalsPhysical Layer Features PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Clock Source Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Magnetics for 1000 BASE-TThird-Party Magnetics Manufacturers Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSerial Eeprom Symbol Ball # Name and functionFunction Default Control options General RegionsManufacturer Size Manufacturers Part Number Eeprom Map InformationSPI EEPROMs for 82575 Ethernet Controller Controller Eeupdate FlashFlash Write Control Flash Erase ControlManufacturer Device SMBus and NC-SIFlash Device Information Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY Power Rail 7uF or 1uF 10uF 2 82575 Ethernet Controller Device Power Supply FilteringUsing Regulators With Enable Pins Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0aPHY Functionality Auto Cross-over for MDI and MDI-X resolution82575 Ethernet Controller Device Test Capability Smartspeed Low-Power Link UpUsing SmartSpeed Flow Control25.6 Reg Link Energy DetectPolarity Correction Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Quartz Crystal Frequency Control Device Design ConsiderationsFrequency Control Component Types Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorCrystal Selection Parameters Vibrational ModeTemperature Stability and Environmental Requirements Nominal FrequencyCalibration Mode Load CapacitanceDrive Level Shunt CapacitanceEquivalent Series Resistance AgingCircuit Board Temperature ChangesReference Crystal Selection This page is intentionally left blank Oscillator Support Oscillator SolutionSpecifications Symbol Parameter Units Min Typical Max VGG=0.6V Rpar =100MΩ Cpar =20pF Layout Considerations for 82575 Ethernet Controllers Guidelines for Component PlacementEthernet Component Layout Guidelines LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingTrace Length and Symmetry for 1000 BASE-T Designs Signal Trace Geometry for 1000 BASE-T DesignsSignal Termination and Coupling Routing 1.8 V to the Magnetics Center Tap Signal IsolationSignal Detect Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsThermal Design Considerations Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Symbol Design and Layout ChecklistsReference Schematics Thermal Management

317698-001 specifications

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