Intel 317698-001 manual Auto-Negotiation differences between PHY, SerDes and Sgmii

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82575 Ethernet Controller Design Guide

3.6.7Auto-Negotiation differences between PHY, SerDes and SGMII

SGMII protocol includes an auto-negotiation process in order to establish the MAC - PHY connection. This auto-negotiation process is not dependent on the SRDS0/

1_SIG_DET signal, as this signal indicates the status of the PHY signal detection (usually used in Optical PHY).

The following shows the outcome of this auto-negotiation process:

•Link status

•Speed

•Duplex.

This information is used by the hardware to configure the MAC, when operating in SGMII mode.

For SerDes and SGMII modes, bits FD and LU of the Device Status register (STATUS), and bits in the PCS_LSTS register provide status information regarding the negotiated link.

•Auto-Negotiation may be initiated by the following:

•LRST transition from 1 to 0

•PCS_LCMD.AN_ENABLE transition from 0 to 1

•Receipt of /C/ ordered set during normal operation

•Receipt of different value of the /C/ ordered set during the negotiation process

•Transition from loss of synchronization to synchronized state (if AN_ENABLE is set).

•PCS_LCMD.AN_RESTART transition from 0 to 1

Resolution of the negotiated link determines device operation with respect to speed and duplex settings. These negotiated capabilities override advertised and software- controlled device configuration.

When working in SGMII mode, there is no need for setting of the PCAS_ANADV register, as the MAC advertisement word is fixed. The result of the SGMII level auto- negotiation can be read from the PCS_LPAB register.

3.6.8Copper PHY Link Configuration

When operating with the internal PHY, link configuration is generally determined by PHY Auto-Negotiation. The driver must intervene in cases where a successful link is not negotiated or the user desires to manually configure the link.

PHY Auto-Negotiation (Speed, Duplex, Flow-Control) when using a copper PHY, the PHY performs the Auto-Negotiation function. Auto-Negotiation provides a method for two link partners to exchange information in a systematic manner in order to establish a link configuration providing the highest common level of functionality supported by both partners. Once configured, the link partners exchange configuration information to resolve link settings such as:

•Speed: 10/100/1000 Mb/s

•Duplex: Full- or Half-

•Flow Control Operation

PHY specific information required for establishing the link is also exchanged.

Note: If flow control is enabled, the settings for the desired flow control behavior must be set by software in the PHY registers and Auto-Negotiation restarted. After Auto-Negotiation

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents PCI Express Port Connection to the Device Other PCI Express SignalsPhysical Layer Features Link Width ConfigurationLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank Magnetics for 1000 BASE-T Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Clock SourceManufacturer Part Number Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Third-Party Magnetics ManufacturersPCI Function # Select PCI/LAN Function IndexGeneral Regions Symbol Ball # Name and functionFunction Default Control options Serial EepromSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Flash EeupdateFlash Erase Control Flash Write ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power Management82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Flow Control Low-Power Link UpUsing SmartSpeed SmartspeedPolarity Correction Link Energy Detect25.6 Reg Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Fixed Crystal Oscillator Frequency Control Device Design ConsiderationsFrequency Control Component Types Quartz CrystalCeramic Resonator Programmable Crystal OscillatorsNominal Frequency Vibrational ModeTemperature Stability and Environmental Requirements Crystal Selection ParametersLoad Capacitance Calibration ModeAging Shunt CapacitanceEquivalent Series Resistance Drive LevelReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Impedance Discontinuities Signal IsolationSignal Detect Routing 1.8 V to the Magnetics Center TapTraces for Decoupling Capacitors Power and Ground PlanesConformance Tests for 10/100/1000 Mbps Designs Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Thermal Design ConsiderationsEthernet Controller Design Guide Thermal Management Design and Layout ChecklistsReference Schematics Symbol

317698-001 specifications

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