Intel 317698-001 manual Link Energy Detect, Polarity Correction, 25.6 Reg

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82575 Ethernet Controller Design Guide

The table below summarizes link speed as function of power management state, link speed control, and gigabit speed enabling:

 

 

Gigabit disable bits

 

Power

Low Power

Disable

 

Disable

 

 

 

Link Up

 

1000 in

PHY speed

Management

1000 (reg

 

(reg 25.1

 

non-D0a

negotiation

State

25.6)

 

& 2)

 

(reg 25.3)

 

 

 

 

 

 

 

 

 

 

PHY negotiates to

 

 

0

 

 

highest speed

 

 

 

 

advertised ("normal

 

 

 

 

 

 

 

 

 

 

operation")

 

0

 

 

X

PHY negotiates to

 

 

 

 

 

highest speed

 

 

1

 

 

advertised ("normal

 

 

 

 

 

operation"), excluding

 

 

 

 

 

1000

D0a

 

 

 

 

PHY goes through Low

 

 

0

 

 

Power Link Up (LPLU)

 

 

 

 

procedure, starting

 

 

 

 

 

 

 

 

 

 

with advertised values

 

1

 

 

X

PHY goes through

 

 

 

 

 

 

LPLU procedure,

 

 

 

 

 

 

 

1

 

 

starting with

 

 

 

 

advertised values.

 

 

 

 

 

 

 

 

 

 

Does not advertise

 

 

 

 

 

1000

 

 

 

 

 

PHY negotiates to

 

 

0

 

0

highest speed

 

 

 

 

 

advertised

 

0

0

 

1

PHY negotiates to

 

 

1

 

X

highest speed

 

 

 

advertised, excluding

Non-D0a

 

 

 

 

1000

 

 

 

 

PHY goes through

 

 

 

 

 

 

 

0

 

0

LPLU procedure,

 

 

 

 

 

starting at 10

 

1

 

 

 

PHY goes through

 

 

0

 

1

LPLU procedure,

 

 

 

starting at 10. Does

 

 

 

 

 

 

 

 

 

 

not advertise 1000

3.6.5Link Energy Detect

The PHY de-asserts the Link Energy Detect Bit (PHYREG 25.4) whenever energy is not detected on the link. This bit provides an indication of a cable becoming plugged or unplugged.

This bit is valid only if auto-negotiation is enabled.

In order to correctly deduce that there is no energy, this bit must read as zero for three consecutive reads each second.

3.6.6Polarity Correction

The PHY automatically detects and corrects for the condition where the receive signal (MDI_PLUS_0/MDI_MINUS_0) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-of-frame markers, are received consecutively. If link pulses or data are not received for 96-130 ms, the polarity state is reset to a non-inverted state.

Automatic polarity correction may be disabled by setting Bit PHYREG.27.5

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Link Width Configuration Other PCI Express SignalsPhysical Layer Features PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Clock Source Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Magnetics for 1000 BASE-TThird-Party Magnetics Manufacturers Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSerial Eeprom Symbol Ball # Name and functionFunction Default Control options General RegionsEeprom Map Information SPI EEPROMs for 82575 Ethernet Controller ControllerManufacturer Size Manufacturers Part Number Eeupdate FlashFlash Write Control Flash Erase ControlSMBus and NC-SI Flash Device InformationManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY 2 82575 Ethernet Controller Device Power Supply Filtering Using Regulators With Enable PinsPower Rail 7uF or 1uF 10uF Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0aAuto Cross-over for MDI and MDI-X resolution 82575 Ethernet Controller Device Test CapabilityPHY Functionality Smartspeed Low-Power Link UpUsing SmartSpeed Flow ControlLink Energy Detect Polarity Correction25.6 Reg Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Quartz Crystal Frequency Control Device Design ConsiderationsFrequency Control Component Types Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorCrystal Selection Parameters Vibrational ModeTemperature Stability and Environmental Requirements Nominal FrequencyCalibration Mode Load CapacitanceDrive Level Shunt CapacitanceEquivalent Series Resistance AgingTemperature Changes Reference Crystal SelectionCircuit Board This page is intentionally left blank Oscillator Solution Specifications Symbol Parameter Units Min Typical MaxOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Guidelines for Component Placement Ethernet Component Layout GuidelinesLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingSignal Trace Geometry for 1000 BASE-T Designs Signal Termination and CouplingTrace Length and Symmetry for 1000 BASE-T Designs Routing 1.8 V to the Magnetics Center Tap Signal IsolationSignal Detect Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsThermal Design Considerations Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Symbol Design and Layout ChecklistsReference Schematics Thermal Management

317698-001 specifications

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