Intel 317698-001 manual Flash, Eeupdate

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82575 Ethernet Controller Design Guide

Table 5. 82575 Ethernet Controller EEPROM Memory Layout

0

MAC address + SW Area

0xA

HW Area

0X30

PXE Area

0x40

Reserved

0x50

FW pointers

FW structures

PCIE/PHY/PLL/SerDes structures

3.2.3.1EEUPDATE

Intel has an MS-DOS* software utility called EEUPDATE, which can be used to program EEPROM images in development or production line environments. To obtain a copy of this program, contact your Intel representative.

3.2.4FLASH

The 82575 Ethernet Controller provides two different methods for software access to the Flash.

Using the legacy Flash transactions the Flash is read from, or written to, whenever the host CPU performs a read or a write operation to a memory location that is within the FLASH address mapping.

Upon boot via accesses in the space indicated by the Expansion ROM Base Address Register.

All accesses to the Flash require the appropriate command sequence for the device used. Refer to the specific Flash data sheet for more details on reading from or writing to Flash. Accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in either:

1. 82575 Flash Base Address Register (PCIe Control Register at offset 14h or 18h).

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Link Width Configuration Other PCI Express SignalsPhysical Layer Features PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Clock Source Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Magnetics for 1000 BASE-TThird-Party Magnetics Manufacturers Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSerial Eeprom Symbol Ball # Name and functionFunction Default Control options General RegionsEeprom Map Information SPI EEPROMs for 82575 Ethernet Controller ControllerManufacturer Size Manufacturers Part Number Eeupdate FlashFlash Write Control Flash Erase ControlSMBus and NC-SI Flash Device InformationManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY 2 82575 Ethernet Controller Device Power Supply Filtering Using Regulators With Enable PinsPower Rail 7uF or 1uF 10uF Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0aAuto Cross-over for MDI and MDI-X resolution 82575 Ethernet Controller Device Test CapabilityPHY Functionality Smartspeed Low-Power Link UpUsing SmartSpeed Flow ControlLink Energy Detect Polarity Correction25.6 Reg Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Quartz Crystal Frequency Control Device Design ConsiderationsFrequency Control Component Types Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorCrystal Selection Parameters Vibrational ModeTemperature Stability and Environmental Requirements Nominal FrequencyCalibration Mode Load CapacitanceDrive Level Shunt CapacitanceEquivalent Series Resistance AgingTemperature Changes Reference Crystal SelectionCircuit Board This page is intentionally left blank Oscillator Solution Specifications Symbol Parameter Units Min Typical MaxOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Guidelines for Component Placement Ethernet Component Layout GuidelinesLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingSignal Trace Geometry for 1000 BASE-T Designs Signal Termination and CouplingTrace Length and Symmetry for 1000 BASE-T Designs Routing 1.8 V to the Magnetics Center Tap Signal IsolationSignal Detect Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsThermal Design Considerations Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Symbol Design and Layout ChecklistsReference Schematics Thermal Management

317698-001 specifications

The Intel 317698-001 is a prominent and highly regarded component in the realm of computer hardware. This product is part of Intel's extensive portfolio, designed primarily for enhancing computing performance, efficiency, and reliability. It is typically associated with server motherboards and is known for its robust architecture, making it ideal for enterprise-level applications.

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