Intel 317698-001 manual Ethernet Controller Device Test Capability, PHY Functionality

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82575 Ethernet Controller Design Guide

3.582575 Ethernet Controller Device Test Capability

The 82575 Ethernet Controller Gigabit Ethernet Controller contains a test access port (3.3 V only) conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these balls to pads accessible by your test equipment.

A BSDL (Boundary Scan Definition Language) file describing the 82575 Ethernet Controller device is available for use in your test environment.

The controller also contains an XOR test tree mechanism for simple board tests. Details of XOR tree operation are available from your Intel representative.

Information about how to obtain test models is available from your Intel representative.

3.6PHY Functionality

This section describes various functions of the PHY.

3.6.1Auto Cross-over for MDI and MDI-X resolution

Twisted pair Ethernet PHY's must be correctly configured for MDI or MDI-X operation to interoperate. The PHY supports the automatic MDI/MDI-X configuration; manual (non- automatic) configuration is still possible by special cable, etc.

For 1000BASE-T links, pair identification is determined automatically in accordance with the standard.

For 10/100 links and during auto-negotiation, pair usage is determined by Bits 12 and 13 in the Port Control Register (PHYREG18).

In addition, the PHY has an Automatic Crossover Detection function. If Bit 18.12 = 1, the PHY automatically detects which application is being used and configures itself accordingly

 

 

 

Flat Cable

 

 

TX

A

TX

RX

A

TX

RX

B

RX

TX

B

RX

PHY

 

RJ45

 

RJ45

 

TX

C

TX

RX

C

RX

RX D

RX

TX

D

TX

MDI (DTE/NIC)

 

MDIX (switch)

Cross (1:0)=00

 

Cross (1:0)=01

22

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Contents Intel 82575 Gigabit Ethernet Controller Design GuidePage Contents Design and Layout Checklists Revision History Date Revision DescriptionThis page intentionally left blank Introduction ScopeReference Documents Other PCI Express Signals Physical Layer FeaturesLink Width Configuration PCI Express Port Connection to the DevicePolarity Inversion Lane ReversalPCI Express Routing Lane Reversal supported modesThis page left intentionally blank Ethernet Component Design Guidelines General Design Considerations for Ethernet ControllersClock Source Magnetics for 1000 BASE-TDesigning with the 82575/EB/ES Gigabit Ethernet Controller Modules for 1000 BASE-T EthernetThird-Party Magnetics Manufacturers Manufacturer Part NumberPCI/LAN Function Index PCI Function # SelectSymbol Ball # Name and function Function Default Control optionsSerial Eeprom General RegionsSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Eeupdate FlashFlash Write Control Flash Erase ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 1 82575 Ethernet Controller Power Sequencing Vout=1.0v 2AY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF Power Management PCIe Power Management4.2 82575 Ethernet Controller Power Management L0s D0u D0a82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Low-Power Link Up Using SmartSpeedSmartspeed Flow ControlPolarity Correction Link Energy Detect25.6 Reg Copper PHY Link Configuration Auto-Negotiation differences between PHY, SerDes and SgmiiCopper/Fiber Switch SerDes-Detect Mode PHY is activeDevice Disable Internal PHY-to-SerDes TransitionSoftware-Definable Pins SDPs Bios handling of Device DisableEthernet Controller Design Guide Frequency Control Device Design Considerations Frequency Control Component TypesQuartz Crystal Fixed Crystal OscillatorProgrammable Crystal Oscillators Ceramic ResonatorVibrational Mode Temperature Stability and Environmental RequirementsCrystal Selection Parameters Nominal FrequencyCalibration Mode Load CapacitanceShunt Capacitance Equivalent Series ResistanceDrive Level AgingReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystals and Oscillators Crystal layout considerationsBoard Stack Up Recommendations CrystalDifferential Pair Trace Routing for 10/100/1000 Designs Trace RoutingSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Signal Isolation Signal DetectRouting 1.8 V to the Magnetics Center Tap Impedance DiscontinuitiesPower and Ground Planes Traces for Decoupling CapacitorsPhysical Layer Conformance Testing Troubleshooting Common Physical Layout IssuesThermal Design Considerations Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Design and Layout Checklists Reference SchematicsSymbol Thermal Management

317698-001 specifications

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