Intel 317698-001 manual 1 82575 Ethernet Controller Power Sequencing, Vout=1.0v 2A

Page 23

82575 Ethernet Controller Design Guide

The 1.8 V rail has a lower current requirement; however, the use of a SVR is still recommended for adequate margin. Using an LVR in this application is acceptable as long as adequate margin exists in the design, and sequencing can be controlled. Figure 3 shows an example of a compact low-part -count LVR that could be used for the 1.8 V supply.

VCC3V3

VCC1V8_LINEAR

 

 

 

 

 

 

Vout=1.8v

C30

 

 

 

10u

U1

 

 

 

Y

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

3

Vin

2

 

1

 

 

 

 

 

 

 

Vout

Adj

Vout

 

 

4

 

 

 

 

 

 

 

Y

R70

470 Y

C29

22u

R69 Y

200 Y

GND

<<Regulator Resistor Selection>> Vout=Vfb*(1+(Rdown/Rup))+(Iadj*Rdown) When Rdown=200ohm: Rup=(200)/(((1.8-(55u*200))/1.25)-1)=464=~470ohm

3.3v -> 1.8v Linear Regulator

82575 _VCC1V8

Change to 1.2Kohm

 

For 82575

VCC1V0_LINEAR

VCC3V3

R80 0 N

1206

For 3.3v input Change Vfb Resistors

1206

R77

0

 

Y

 

C47

R68

R47

X5R

2.2u

0

100K

 

Y

Y

Y

 

 

 

R67

0 N

U3

2

IN1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

IN2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

IN3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

IN4

 

 

 

 

 

 

 

 

 

GND EPAD

1

 

EN

 

6

POK

 

 

 

 

 

 

 

 

8

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUT1

OUT2

OUT3

OUT4

FB

TP1

TP2

Vout=1.0v (2A)

10

11X5R

12

R45

C39

13

1K

10u

 

Y

X5R

9

 

Y

 

C38

7

R46

10u

14

Y

 

1K

 

 

 

Y

 

GND

<<Regulator Resistor Selection>> Vout=Vfb*(1+(Rup/Rdown)) Rup=((Vout/Vfb)-1)*Rdown Rup=((1.0/0.5)-1)*1K=1Kohm

1.8v -> 1.0v Linear Regulator

Should be

<5Kohm

Figure 4. Example of Linear Voltage Regulator for 1.8 V power rail

3.4.182575 Ethernet Controller Power Sequencing

Regardless of which type of regulator used, all regulators need to adhere to the sequencing shown in Figure 5 to avoid latch-up and forward-biased internal diodes.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents PCI Express Port Connection to the Device Other PCI Express SignalsPhysical Layer Features Link Width ConfigurationLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank Magnetics for 1000 BASE-T Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Clock SourceManufacturer Part Number Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Third-Party Magnetics ManufacturersPCI Function # Select PCI/LAN Function IndexGeneral Regions Symbol Ball # Name and functionFunction Default Control options Serial EepromManufacturer Size Manufacturers Part Number Eeprom Map InformationSPI EEPROMs for 82575 Ethernet Controller Controller Flash EeupdateFlash Erase Control Flash Write ControlManufacturer Device SMBus and NC-SIFlash Device Information Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Power Rail 7uF or 1uF 10uF 2 82575 Ethernet Controller Device Power Supply FilteringUsing Regulators With Enable Pins PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power ManagementPHY Functionality Auto Cross-over for MDI and MDI-X resolution82575 Ethernet Controller Device Test Capability Flow Control Low-Power Link UpUsing SmartSpeed Smartspeed25.6 Reg Link Energy DetectPolarity Correction Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Fixed Crystal Oscillator Frequency Control Device Design ConsiderationsFrequency Control Component Types Quartz CrystalCeramic Resonator Programmable Crystal OscillatorsNominal Frequency Vibrational ModeTemperature Stability and Environmental Requirements Crystal Selection ParametersLoad Capacitance Calibration ModeAging Shunt CapacitanceEquivalent Series Resistance Drive LevelCircuit Board Temperature ChangesReference Crystal Selection This page is intentionally left blank Oscillator Support Oscillator SolutionSpecifications Symbol Parameter Units Min Typical Max VGG=0.6V Rpar =100MΩ Cpar =20pF Layout Considerations for 82575 Ethernet Controllers Guidelines for Component PlacementEthernet Component Layout Guidelines LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsTrace Length and Symmetry for 1000 BASE-T Designs Signal Trace Geometry for 1000 BASE-T DesignsSignal Termination and Coupling Impedance Discontinuities Signal IsolationSignal Detect Routing 1.8 V to the Magnetics Center TapTraces for Decoupling Capacitors Power and Ground PlanesConformance Tests for 10/100/1000 Mbps Designs Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Thermal Design ConsiderationsEthernet Controller Design Guide Thermal Management Design and Layout ChecklistsReference Schematics Symbol

317698-001 specifications

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