Intel 317698-001 manual Ethernet Controller Design Guide

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82575 Ethernet Controller Design Guide

Note: To avoid signal contention, all four pins are set as input pins until after EEPROM configuration has been loaded.

In addition to all four pins being individually configurable as inputs or outputs, they may be configured for use as general-purpose interrupt (GPI) inputs. To act as GPI pins, the desired pins must be configured as inputs. A separate GPI interrupt-detection enable is then used to enable rising-edge detection of the input pin (rising-edge detection occurs by comparing values sampled at 62.5 MHz, as opposed to an edge- detection circuit). When detected, a corresponding GPI interrupt is indicated in the Interrupt Cause register.

The use, direction, and values of SDPs are controlled and accessed using fields in the Device Control Register (CTRL) and Extended Device Control Register (CTRL_EXT).

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents PCI Express Port Connection to the Device Other PCI Express SignalsPhysical Layer Features Link Width ConfigurationLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank Magnetics for 1000 BASE-T Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Clock SourceManufacturer Part Number Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Third-Party Magnetics ManufacturersPCI Function # Select PCI/LAN Function IndexGeneral Regions Symbol Ball # Name and functionFunction Default Control options Serial EepromManufacturer Size Manufacturers Part Number Eeprom Map InformationSPI EEPROMs for 82575 Ethernet Controller Controller Flash EeupdateFlash Erase Control Flash Write ControlManufacturer Device SMBus and NC-SIFlash Device Information Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Power Rail 7uF or 1uF 10uF 2 82575 Ethernet Controller Device Power Supply FilteringUsing Regulators With Enable Pins PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power ManagementPHY Functionality Auto Cross-over for MDI and MDI-X resolution82575 Ethernet Controller Device Test Capability Flow Control Low-Power Link UpUsing SmartSpeed Smartspeed25.6 Reg Link Energy DetectPolarity Correction Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Fixed Crystal Oscillator Frequency Control Device Design ConsiderationsFrequency Control Component Types Quartz CrystalCeramic Resonator Programmable Crystal OscillatorsNominal Frequency Vibrational ModeTemperature Stability and Environmental Requirements Crystal Selection ParametersLoad Capacitance Calibration ModeAging Shunt CapacitanceEquivalent Series Resistance Drive LevelCircuit Board Temperature ChangesReference Crystal Selection This page is intentionally left blank Oscillator Support Oscillator SolutionSpecifications Symbol Parameter Units Min Typical Max VGG=0.6V Rpar =100MΩ Cpar =20pF Layout Considerations for 82575 Ethernet Controllers Guidelines for Component PlacementEthernet Component Layout Guidelines LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsTrace Length and Symmetry for 1000 BASE-T Designs Signal Trace Geometry for 1000 BASE-T DesignsSignal Termination and Coupling Impedance Discontinuities Signal IsolationSignal Detect Routing 1.8 V to the Magnetics Center TapTraces for Decoupling Capacitors Power and Ground PlanesConformance Tests for 10/100/1000 Mbps Designs Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Thermal Design ConsiderationsEthernet Controller Design Guide Thermal Management Design and Layout ChecklistsReference Schematics Symbol

317698-001 specifications

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