Intel 317698-001 manual Reference Crystal Selection, Circuit Board, Temperature Changes

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82575 Ethernet Controller Design Guide

Even with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than the exact center of the target frequency. Therefore, frequency measurements (which determine the correct value for C1 and C2) should be performed with an ideal reference crystal. When the capacitive load is exactly equal to the crystal’s load rating, an ideal reference crystal will be perfectly centered at the desired target frequency.

5.11.1Reference Crystal Selection

There are several methods available for choosing the appropriate reference crystal:

If a Saunders and Associates (S&A) crystal network analyzer is available, then discrete crystal components can be tested until one is found with zero or nearly zero ppm deviation (with the appropriate capacitive load). A crystal with zero or near zero ppm deviation will be a good reference crystal to use in subsequent frequency tests to determine the best values for C1 and C2.

If a crystal analyzer is not available, then the selection of a reference crystal can be done by measuring a statistically valid sample population of crystals, which has units from multiple lots and approved vendors. The crystal, which has an oscillation frequency closest to the center of the distribution, should be the reference crystal used during testing to determine the best values for C1 and C2.

It may also be possible to ask the approved crystal vendors or manufacturers to provide a reference crystal with zero or nearly zero deviation from the specified frequency when it has the specified CLoad capacitance.

When choosing a crystal, customers must keep in mind that to comply with IEEE specifications for 10/100 and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be precise within ±50 ppm. Intel® recommends customers to use a transmitter reference frequency that is accurate to within ±30 ppm to account for variations in crystal accuracy due to crystal manufacturing tolerance..

5.11.2Circuit Board

Since the dielectric layers of the circuit board are allowed some reasonable variation in thickness, the stray capacitance from the printed board (to the crystal circuit) will also vary. If the thickness tolerance for the outer layers of dielectric are controlled within ±17 percent of nominal, then the circuit board should not cause more than ±2 pF variation to the stray capacitance at the crystal. When tuning crystal frequency, it is recommended that at least three circuit boards are tested for frequency. These boards should be from different production lots of bare circuit boards.

Alternatively, a larger sample population of circuit boards can be used. A larger population will increase the probability of obtaining the full range of possible variations in dielectric thickness and the full range of variation in stray capacitance.

Next, the exact same crystal and discrete load capacitors (C1 and C2) must be soldered onto each board, and the LAN reference frequency should be measured on each circuit board.

The circuit board, which has a LAN reference frequency closest to the center of the frequency distribution, should be used while performing the frequency measurements to select the appropriate value for C1 and C2.

5.11.3Temperature Changes

Temperature changes can cause the crystal frequency to shift. Therefore, frequency measurements should be done in the final system chassis across the system’s rated operating temperature range.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents Physical Layer Features Other PCI Express SignalsLink Width Configuration PCI Express Port Connection to the DeviceLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank General Design Considerations for Ethernet Controllers Ethernet Component Design GuidelinesClock Source Magnetics for 1000 BASE-TModules for 1000 BASE-T Ethernet Designing with the 82575/EB/ES Gigabit Ethernet ControllerThird-Party Magnetics Manufacturers Manufacturer Part NumberPCI Function # Select PCI/LAN Function IndexFunction Default Control options Symbol Ball # Name and functionSerial Eeprom General RegionsManufacturer Size Manufacturers Part Number Eeprom Map InformationSPI EEPROMs for 82575 Ethernet Controller Controller Flash EeupdateFlash Erase Control Flash Write ControlManufacturer Device SMBus and NC-SIFlash Device Information Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Power Rail 7uF or 1uF 10uF 2 82575 Ethernet Controller Device Power Supply FilteringUsing Regulators With Enable Pins PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power ManagementPHY Functionality Auto Cross-over for MDI and MDI-X resolution82575 Ethernet Controller Device Test Capability Using SmartSpeed Low-Power Link UpSmartspeed Flow Control25.6 Reg Link Energy DetectPolarity Correction Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Frequency Control Component Types Frequency Control Device Design ConsiderationsQuartz Crystal Fixed Crystal OscillatorCeramic Resonator Programmable Crystal OscillatorsTemperature Stability and Environmental Requirements Vibrational ModeCrystal Selection Parameters Nominal FrequencyLoad Capacitance Calibration ModeEquivalent Series Resistance Shunt CapacitanceDrive Level AgingCircuit Board Temperature ChangesReference Crystal Selection This page is intentionally left blank Oscillator Support Oscillator SolutionSpecifications Symbol Parameter Units Min Typical Max VGG=0.6V Rpar =100MΩ Cpar =20pF Layout Considerations for 82575 Ethernet Controllers Guidelines for Component PlacementEthernet Component Layout Guidelines LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsTrace Length and Symmetry for 1000 BASE-T Designs Signal Trace Geometry for 1000 BASE-T DesignsSignal Termination and Coupling Signal Detect Signal IsolationRouting 1.8 V to the Magnetics Center Tap Impedance DiscontinuitiesTraces for Decoupling Capacitors Power and Ground PlanesTroubleshooting Common Physical Layout Issues Physical Layer Conformance TestingThermal Design Considerations Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Reference Schematics Design and Layout ChecklistsSymbol Thermal Management

317698-001 specifications

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