Intel 317698-001 manual Flash Write Control, Flash Erase Control

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82575 Ethernet Controller Design Guide

2.A particular address range of the IOADDR register defined by the IO Base Address Register (PCIe Control Register at offset 18h or 20h).

3.The Expansion ROM Base Address Register (PCIe Control Register at offset 30h).

The 82575 controls accesses to the Flash when it decodes a valid access.

Note: Flash read accesses must always be assembled by the 82575 whenever the access is greater than a byte-wide access.

Note: Byte reads or writes to the Flash take on the order of 2us. The device will continue to issue retry accesses during this time.

Note: The 82575 Ethernet Controller supports only byte writes to the Flash.

Another way for SW to access the Flash is directly using the Flash's 4-wire interface through the Flash Access Register (FLA). It can use this for reads, writes, or other Flash operations (accessing the Flash status register, erase…).

To directly access the Flash, software should follow these steps:

1.Write a 1 to the Flash Request bit (FLA.FL_REQ)

2.Read the Flash Grant bit (FLA.FL_GNT) until it becomes 1. It will remain 0 as long as there are other accesses to the Flash.

3.Write or read the Flash using the direct access to the 4-wire interface as defined in the Flash Access Register (FLA). The exact protocol used depends on the Flash placed on the board and can be found in the appropriate datasheet.

4.Write a 0 to the Flash Request bit (FLA.FL_REQ).

3.2.4.1Flash Write Control

The Flash is write controlled by the FWE bits in the EEPROM/FLASH Control and Data Register (EEC). Note that attempts to write to the Flash device when writes are disabled (FWE10) should not be attempted. Behavior after such an operation is undefined, and may result in component and/or system hangs.

After sending one byte write to the flash, the software can check if it can send the next byte to write (check if the write process in the Flash had finished) by reading the Flash Access Register. If bit (FLA.FL_BUSY) in this register is set, the current write did not finish. If bit (FLA.FL_BUSY) is clear, then the software can continue and write the next byte to the Flash.

3.2.4.2Flash Erase Control

When software wants to erase the Flash, it should set bit FLA.FL_ER in the Flash Access Register to one (Flash erase and set bits EEC.FWE in the EEPROM/Flash Control Register to zero).

The hardware will get this command and send the erase command to the Flash. The erase process will finish by itself. Software should wait for the end of the erase process before any further access to the flash. This can be checked by using the Flash Write control mechanism described earlier.

The op-code used for erase operation is defined in the FLASHOP register.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents PCI Express Port Connection to the Device Other PCI Express SignalsPhysical Layer Features Link Width ConfigurationLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank Magnetics for 1000 BASE-T Ethernet Component Design GuidelinesGeneral Design Considerations for Ethernet Controllers Clock SourceManufacturer Part Number Designing with the 82575/EB/ES Gigabit Ethernet ControllerModules for 1000 BASE-T Ethernet Third-Party Magnetics ManufacturersPCI Function # Select PCI/LAN Function IndexGeneral Regions Symbol Ball # Name and functionFunction Default Control options Serial EepromSPI EEPROMs for 82575 Ethernet Controller Controller Eeprom Map InformationManufacturer Size Manufacturers Part Number Flash EeupdateFlash Erase Control Flash Write ControlFlash Device Information SMBus and NC-SIManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Using Regulators With Enable Pins 2 82575 Ethernet Controller Device Power Supply FilteringPower Rail 7uF or 1uF 10uF PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power Management82575 Ethernet Controller Device Test Capability Auto Cross-over for MDI and MDI-X resolutionPHY Functionality Flow Control Low-Power Link UpUsing SmartSpeed SmartspeedPolarity Correction Link Energy Detect25.6 Reg Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Fixed Crystal Oscillator Frequency Control Device Design ConsiderationsFrequency Control Component Types Quartz CrystalCeramic Resonator Programmable Crystal OscillatorsNominal Frequency Vibrational ModeTemperature Stability and Environmental Requirements Crystal Selection ParametersLoad Capacitance Calibration ModeAging Shunt CapacitanceEquivalent Series Resistance Drive LevelReference Crystal Selection Temperature ChangesCircuit Board This page is intentionally left blank Specifications Symbol Parameter Units Min Typical Max Oscillator SolutionOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Ethernet Component Layout Guidelines Guidelines for Component PlacementLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsSignal Termination and Coupling Signal Trace Geometry for 1000 BASE-T DesignsTrace Length and Symmetry for 1000 BASE-T Designs Impedance Discontinuities Signal IsolationSignal Detect Routing 1.8 V to the Magnetics Center TapTraces for Decoupling Capacitors Power and Ground PlanesConformance Tests for 10/100/1000 Mbps Designs Physical Layer Conformance TestingTroubleshooting Common Physical Layout Issues Thermal Design ConsiderationsEthernet Controller Design Guide Thermal Management Design and Layout ChecklistsReference Schematics Symbol

317698-001 specifications

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