Intel 317698-001 Eeprom Map Information, SPI EEPROMs for 82575 Ethernet Controller Controller

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82575 Ethernet Controller Design Guide

Legacy Wake On LAN (magic packets) is not supported

All the initializations normally loaded from the EEPROM will be loaded by the host driver.

For more information, see the 82575 Gigabit Ethernet Controller Software Developer's Manual and the 82575 EEPROM Information Guide Application Note AP-499.

3.2.2.3SPI EEPROMs for 82575 Ethernet Controller Controller

SPI EEPROMs that have been found to work satisfactorily with the 82575 device are listed in Table 4. SPI EEPROMs must be rated for a clock rate of at least 2 MHz.

Table 4.

SPI EEPROMs for 82575 Ethernet Controller Controller

 

 

 

 

 

 

 

 

 

Manufacturer

 

Size

Manufacturer's Part

 

 

 

Number

 

 

 

 

 

 

 

 

 

 

 

 

Catalyst

 

32Kb

 

25C32S 0113A

 

 

 

 

 

 

 

Catalyst

 

8Kb

 

25C08S

 

 

 

 

 

 

 

Catalyst

 

64Kb

 

25C64S 0139B

 

 

 

 

 

 

 

STM

 

256Kb

 

95256W6 K350V

 

 

 

 

 

 

 

STM

 

64Kb

 

95640W6

 

 

 

 

 

 

 

STM

 

32Kb

 

95320W6

 

 

 

 

 

 

 

STM

 

16Kb

 

95160W6

 

 

 

 

 

 

 

STM

 

8Kb

 

95080W6

 

 

 

 

 

 

 

Motorola

 

64Kb

 

25AA640

 

 

 

 

 

 

 

Motorola

 

32kb

 

25AA320

 

 

 

 

 

 

 

Motorola

 

16Kb

 

25AA160A

 

 

 

 

 

 

Note: Use a 128 kbit EEPROM for all applications until an appropriate size for each application is determined. Recommended manufacturer and part numbers are Atmel’s AT25128N or Microchip’s 25LC128.

For more information on the various management options refer to Intel’s Application Note 459, 82573/82572/82571/ESB2/82575 LAN Total Cost of Ownership (TCO) System Management Bus Interface.

3.2.3EEPROM Map Information

The table below summarizes the EEPROM map for the 82575 Ethernet Controller Gigabit Ethernet Controller. For more about the using an EEPROM, see the 82575 Ethernet Controller EEPROM Map and Programming Information Guide, Application Note (AP-nnn).

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents Physical Layer Features Other PCI Express SignalsLink Width Configuration PCI Express Port Connection to the DeviceLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank General Design Considerations for Ethernet Controllers Ethernet Component Design GuidelinesClock Source Magnetics for 1000 BASE-TModules for 1000 BASE-T Ethernet Designing with the 82575/EB/ES Gigabit Ethernet ControllerThird-Party Magnetics Manufacturers Manufacturer Part NumberPCI Function # Select PCI/LAN Function IndexFunction Default Control options Symbol Ball # Name and functionSerial Eeprom General RegionsManufacturer Size Manufacturers Part Number Eeprom Map InformationSPI EEPROMs for 82575 Ethernet Controller Controller Flash EeupdateFlash Erase Control Flash Write ControlManufacturer Device SMBus and NC-SIFlash Device Information Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY Power Rail 7uF or 1uF 10uF 2 82575 Ethernet Controller Device Power Supply FilteringUsing Regulators With Enable Pins PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power ManagementPHY Functionality Auto Cross-over for MDI and MDI-X resolution82575 Ethernet Controller Device Test Capability Using SmartSpeed Low-Power Link UpSmartspeed Flow Control25.6 Reg Link Energy DetectPolarity Correction Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Frequency Control Component Types Frequency Control Device Design ConsiderationsQuartz Crystal Fixed Crystal OscillatorCeramic Resonator Programmable Crystal OscillatorsTemperature Stability and Environmental Requirements Vibrational ModeCrystal Selection Parameters Nominal FrequencyLoad Capacitance Calibration ModeEquivalent Series Resistance Shunt CapacitanceDrive Level AgingCircuit Board Temperature ChangesReference Crystal Selection This page is intentionally left blank Oscillator Support Oscillator SolutionSpecifications Symbol Parameter Units Min Typical Max VGG=0.6V Rpar =100MΩ Cpar =20pF Layout Considerations for 82575 Ethernet Controllers Guidelines for Component PlacementEthernet Component Layout Guidelines LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsTrace Length and Symmetry for 1000 BASE-T Designs Signal Trace Geometry for 1000 BASE-T DesignsSignal Termination and Coupling Signal Detect Signal IsolationRouting 1.8 V to the Magnetics Center Tap Impedance DiscontinuitiesTraces for Decoupling Capacitors Power and Ground PlanesTroubleshooting Common Physical Layout Issues Physical Layer Conformance TestingThermal Design Considerations Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Reference Schematics Design and Layout ChecklistsSymbol Thermal Management

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