Intel 317698-001 manual Ethernet Component Layout Guidelines, Guidelines for Component Placement

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82575 Ethernet Controller Design Guide

7.0Ethernet Component Layout Guidelines

These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements.

7.1Layout Considerations for 82575 Ethernet Controllers

Critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes. Keeping the traces as short as possible can also reduce capacitive loading.

Since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs.

Designing for 1000 BASE-T Gigabit operation is very similar to designing for 10 and 100 Mbps. For the 82575 Gigabit Ethernet controller, system level tests should be performed at all three speeds.

7.1.1Guidelines for Component Placement

Component placement can affect signal quality, emissions, and component operating temperature This section provides guidelines for component placement.

Careful component placement can:

Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet applicable government test specifications.

Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.

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Contents Design Guide Intel 82575 Gigabit Ethernet ControllerPage Contents Design and Layout Checklists Date Revision Description Revision HistoryThis page intentionally left blank Scope IntroductionReference Documents Physical Layer Features Other PCI Express SignalsLink Width Configuration PCI Express Port Connection to the DeviceLane Reversal Polarity InversionLane Reversal supported modes PCI Express RoutingThis page left intentionally blank General Design Considerations for Ethernet Controllers Ethernet Component Design GuidelinesClock Source Magnetics for 1000 BASE-TModules for 1000 BASE-T Ethernet Designing with the 82575/EB/ES Gigabit Ethernet ControllerThird-Party Magnetics Manufacturers Manufacturer Part NumberPCI Function # Select PCI/LAN Function IndexFunction Default Control options Symbol Ball # Name and functionSerial Eeprom General RegionsEeprom Map Information SPI EEPROMs for 82575 Ethernet Controller ControllerManufacturer Size Manufacturers Part Number Flash EeupdateFlash Erase Control Flash Write ControlSMBus and NC-SI Flash Device InformationManufacturer Device Power Supplies for the 82575 Ethernet Controller Controllers Example Switching Voltage Regulator for 1.0 V and 1.8 Vout=1.0v 2A 1 82575 Ethernet Controller Power SequencingY 2 82575 Ethernet Controller Device Power Supply Filtering Using Regulators With Enable PinsPower Rail 7uF or 1uF 10uF PCIe Power Management Power ManagementL0s D0u D0a 4.2 82575 Ethernet Controller Power ManagementAuto Cross-over for MDI and MDI-X resolution 82575 Ethernet Controller Device Test CapabilityPHY Functionality Using SmartSpeed Low-Power Link UpSmartspeed Flow ControlLink Energy Detect Polarity Correction25.6 Reg Auto-Negotiation differences between PHY, SerDes and Sgmii Copper PHY Link ConfigurationSerDes-Detect Mode PHY is active Copper/Fiber SwitchInternal PHY-to-SerDes Transition Device DisableBios handling of Device Disable Software-Definable Pins SDPsEthernet Controller Design Guide Frequency Control Component Types Frequency Control Device Design ConsiderationsQuartz Crystal Fixed Crystal OscillatorCeramic Resonator Programmable Crystal OscillatorsTemperature Stability and Environmental Requirements Vibrational ModeCrystal Selection Parameters Nominal FrequencyLoad Capacitance Calibration ModeEquivalent Series Resistance Shunt CapacitanceDrive Level AgingTemperature Changes Reference Crystal SelectionCircuit Board This page is intentionally left blank Oscillator Solution Specifications Symbol Parameter Units Min Typical MaxOscillator Support VGG=0.6V Rpar =100MΩ Cpar =20pF Guidelines for Component Placement Ethernet Component Layout GuidelinesLayout Considerations for 82575 Ethernet Controllers LAN Layout for Integrated Magnetics Crystal layout considerations Crystals and OscillatorsCrystal Board Stack Up RecommendationsTrace Routing Differential Pair Trace Routing for 10/100/1000 DesignsSignal Trace Geometry for 1000 BASE-T Designs Signal Termination and CouplingTrace Length and Symmetry for 1000 BASE-T Designs Signal Detect Signal IsolationRouting 1.8 V to the Magnetics Center Tap Impedance DiscontinuitiesTraces for Decoupling Capacitors Power and Ground PlanesTroubleshooting Common Physical Layout Issues Physical Layer Conformance TestingThermal Design Considerations Conformance Tests for 10/100/1000 Mbps DesignsEthernet Controller Design Guide Reference Schematics Design and Layout ChecklistsSymbol Thermal Management

317698-001 specifications

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