Spectrum Brands C6x VME64 manual 0x0180

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Monaco Technical Reference	Spectrum Signal Processing
Processor Nodes

Table 4 'C6x Internal Peripheral Register Values

Register Address	Value	Comments

Global Control Register	0x0000 3078	NOHOLD (External HOLD disable) off
0x0180 0000		SDCEN (SDRAM clock enable) on
		SSCEN (SBSRAM clock enable) on
		CLK1EN (CLKOUT1 enable) on
		CLK2EN (CLKOUT2 enable) on
		SSCRT (SBSRAM clock rate select) 1/2x CPU clock
		RBTR8 off (requester controls EMIF until a high priority request
		occurs..
EMIF CE0 Control Register	0xFFFF 3F43	MTYPE = 32 bit wide SBSRAM
0x0180 0008		No other bits are used.

EMIF CE1 Control Register	0x30E4 0421	MTYPE = 32 bit wide asynchronous interface
0x0180 0004		write setup = 3 cycles
		write strobe = 3 cycles
		write hold = 2 cycles
		read setup = 4 cycles
		read strobe = 4 cycles
		read hold = 1 cycle
		all cycles are clockout1 cycles
EMIF CE2 Control Register	0xFFFF 3F33	MTYPE = 32 bit wide SDRAM
0x0180 0010		No other bits are used.

EMIF CE3 Control Register	0x72B7 0A23	MTYPE = 32 bit wide asynchronous interface
(Used for PEM. Must be		address = 0x01800004
reconfigured for individual		value = 0x30E40421
PEM)		MTYPE = 32 bit wide asynchronous interface
0x0180 0014		write setup = 7 cycles
		write strobe = 10 cycles
		write hold = 3 cycles
		read setup = 7 cycles
		read strobe = 10 cycles
		read hold = 3 cycle
		all cycles are clockout1 cycles
EMIF SDRAM Control	0x0544 A000	RFEN = 0 internal refresh enable OFF. Only external SDRAM
0x0180 0018		refresh can be used.
0x0180 0018		SDWID = 1 (SDRAM width select) two 16 bit SDRAMs
		SDWID = 1 (SDRAM width select) two 16 bit SDRAMs
		Other timing parameters are SDRAM specific and should not be
		modified by the user.
EMIF SDRAM Timing	0x0000 061A	Refresh timer implemented in external hardware. This register is
0x0180 001C		not used.
0x0180 001C

12	Part Number 500-00191
	Revision 2.00

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Contents Monaco Revision Preface IiiDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors Interfaces VMEPMC PEMReference Documents On-Board Power Supply General Bus ArchitectureReset Conditions VME A24 Slave Interface ResetJtag Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DSynchronous Burst Sram Synchronous DramProcessor Expansion Module Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortGlobal Shared Bus Access Source Target Global Shared BusMemory ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingPEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc KiplenbDL3RESET DSP~LINK3 RegisterID Register VME A24 Status Register HintaHintb HintcVME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset