Spectrum Brands C6x VME64 manual PEM Connections for Serial Port 0

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Monaco Technical Reference

Spectrum Signal Processing

Processor Nodes

Pin assignments for the serial ports are given in the following tables.

Table 6 PEM Connections for Serial Port 0 and 1

Signal

 

PEM 1 Port 0

PEM 2 Port 1*

 

 

 

 

CLKS

External clock

56

17

 

 

 

 

CLKR

Receive clock

52

13

 

 

 

 

CLKX

Transmit clock

42

3

 

 

 

 

DR

Received serial data

48

9

 

 

 

 

DX

Transmitted serial data

46

7

 

 

 

 

FSR

Receive frame synchronization

50

11

 

 

 

 

FSX

Transmit frame synchronization

44

5

 

 

 

 

*The serial port routing jumper corresponding to the node (J7, J8, J9, or J10) must be OUT for port 1 to be routed to the node’s PEM 2 connector.

Table 7 VME and PMC Connections for Serial Port 1

 

 

Node A (J7 IN)

Node B (J8 IN)

Node C (J9 IN)

Node D (J10 IN)

Signal

 

PMC JN5

VME-P2

PMC JN5

VME-P2

PMC JN5

VME-P2

PMC JN5

VME-P2

 

 

 

 

 

 

 

 

 

 

CLKS

External clock

1

D-4

21

D-18

2

Z-3

22

Z-17

 

 

 

 

 

 

 

 

 

 

CLKR

Receive clock

5

D-6

25

D-20

6

Z-5

26

Z-19

 

 

 

 

 

 

 

 

 

 

CLKX

Transmit clock

9

D-8

29

D-22

10

Z-7

30

Z-21

 

 

 

 

 

 

 

 

 

 

DR

Received serial data

11

D-10

31

D-24

12

Z-9

32

Z-23

 

 

 

 

 

 

 

 

 

 

DX

Transmitted serial data

13

D-12

33

D-26

14

Z-11

34

Z-25

 

 

 

 

 

 

 

 

 

 

FSR

Receive frame synchronization

15

D-14

35

D-28

16

Z-13

36

Z-27

 

 

 

 

 

 

 

 

 

 

FSX

Transmit frame synchronization

17

D-16

37

D-30

18

Z-15

38

Z-29

 

 

 

 

 

 

 

 

 

 

18

Part Number 500-00191

 

Revision 2.00

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Contents Monaco Revision Preface IiiDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PMC InterfacesVME PEMReference Documents On-Board Power Supply General Bus ArchitectureJtag Reset Reset ConditionsVME A24 Slave Interface Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DProcessor Expansion Module Synchronous Burst SramSynchronous Dram Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortMemory Global Shared Bus Access Source TargetGlobal Shared Bus ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingHurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend KiplenbDL3RESET DSP~LINK3 RegisterID Register Hintb VME A24 Status RegisterHinta HintcVME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset