Spectrum Brands C6x VME64 manual VME P2 Connector DSP~LINK3 to VME P2

Page 78

Monaco Technical Reference

Spectrum Signal Processing

Connector Pinouts

Table 18 VME P2 Connector (DSP~LINK3 to VME P2)

Pin #

Z Row Signal

A Row Signal

B Row Signal

C Row Signal

D Row Signal

 

 

 

 

 

 

1

NC

NC

+5V

DL3_A15

NC

 

 

 

 

 

 

2

GND

DL3_A14

GND

DL3_A13

NC

 

 

 

 

 

 

3

CLKS_C1

DL3_A12

NC

DL3_A11

GND

 

 

 

 

 

 

4

GND

DL3_A10

A24

DL3_A9

CLKS_A1

 

 

 

 

 

 

5

CLKR_C1

DL3_A8

A25

DL3_A7

GND

 

 

 

 

 

 

6

GND

DL3_A6

A26

DL3_A5

CLKR_A1

 

 

 

 

 

 

7

CLKX_C1

DL3_A4

A27

DL3_A3

GND

 

 

 

 

 

 

8

GND

DL3_A2

A28

DL3_A1

CLKX_A1

 

 

 

 

 

 

9

DR_C1

DL3_A0

A29

DL3_R/W

GND

 

 

 

 

 

 

10

GND

/DL3_RESET

A30

NC

DR_A1

 

 

 

 

 

 

11

DX_C1

/DL3_DSTRB

A31

NC

GND

 

 

 

 

 

 

12

GND

/DL3_ASTRB

GND

NC

DX_A1

 

 

 

 

 

 

13

FSR_C1

/DL3_RDY

+5V

NC

GND

 

 

 

 

 

 

14

GND

/DL3_INT0

D16

/DL3_INT2

FSR_A1

 

 

 

 

 

 

15

FSX_C1

/DL3_INT1

D17

/DL3_INT3

GND

 

 

 

 

 

 

16

GND

NC

D18

NC

FSX_A1

 

 

 

 

 

 

17

CLKS_D1

DL3_D31

D19

DL3_D30

GND

 

 

 

 

 

 

18

GND

DL3_D29

D20

DL3_D28

CLKS_B1

 

 

 

 

 

 

19

CLKR_D1

DL3_D27

D21

DL3_D26

GND

 

 

 

 

 

 

20

GND

DL3_D25

D22

DL3_D24

CLKR_B1

 

 

 

 

 

 

21

CLKX_D1

DL3_D23

D23

DL3_D22

GND

 

 

 

 

 

 

22

GND

DL3_D21

GND

DL3_D20

CLKX_B1

 

 

 

 

 

 

23

DR_D1

DL3_D19

D24

DL3_D18

GND

 

 

 

 

 

 

24

GND

DL3_D17

D25

DL3_D16

DR_B1

 

 

 

 

 

 

25

DX_D1

DL3_D15

D26

DL3_D14

GND

 

 

 

 

 

 

26

GND

DL3_D13

D27

DL3_D12

DX_B1

 

 

 

 

 

 

27

FSR_D1

DL3_D11

D28

DL3_D10

GND

 

 

 

 

 

 

28

GND

DL3_D9

D29

DL3_D8

FSR_B1

 

 

 

 

 

 

29

FSX_D1

DL3_D7

D30

DL3_D6

GND

 

 

 

 

 

 

30

GND

DL3_D5

D31

DL3_D4

FSX_B1

 

 

 

 

 

 

31

NC

DL3_D3

GND

DL3_D2

NC

 

 

 

 

 

 

32

GND

DL3_D1

+5V

DL3_D0

NC

 

 

 

 

 

 

66

Part Number 500-00191

 

Revision 2.00

Image 78
Contents Monaco Revision Preface IiiDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PMC InterfacesVME PEMReference Documents On-Board Power Supply General Bus ArchitectureJtag Reset Reset ConditionsVME A24 Slave Interface Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DProcessor Expansion Module Synchronous Burst SramSynchronous Dram Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortMemory Global Shared Bus Access Source TargetGlobal Shared Bus ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingHurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend KiplenbDL3RESET DSP~LINK3 RegisterID Register Hintb VME A24 Status RegisterHinta HintcVME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset