Spectrum Brands C6x VME64 manual Hurricane Implementation, PCI Device

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Monaco Technical Reference						Spectrum Signal Processing
PCI Interface

Hurricane	'C6x	PCI Bus	Slave A32/A24	Register	Description		Value	Initialize
DSP Offset	Address	Offset	SCV64 Offset
0x4F	0x016C 013C	0x0020 013C	0x0020 013C				0x0120 0100
0x50	0x016C 0140	0x0020 0140	0x0020 0140		BAR0 Shadow Register		0xFF00 0000	Y

6.2.Hurricane Implementation

The Hurricane PCI-to-DSP Bridge Data Sheet should be read in order to understand how it is used with the Monaco board.

On the DSP port of the Hurricane, only bank 0 is used to access the Global Shared Bus. All other Hurricane DSP banks are unused.

There are two devices on the PMC site’s PCI bus: the Hurricane chip and the PMC device. The IDSEL line from each of the two PCI devices is connected to the following Address/Data lines:

PCI Device	IDSEL Connection
Hurricane	AD16
PMC Module	AD17

36	Part Number 500-00191
	Revision 2.00

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Contents Monaco Revision Preface IiiDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors Interfaces VMEPMC PEMReference Documents On-Board Power Supply General Bus ArchitectureReset Conditions VME A24 Slave Interface ResetJtag Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DSynchronous Burst Sram Synchronous DramProcessor Expansion Module Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortGlobal Shared Bus Access Source Target Global Shared BusMemory ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingPEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc KiplenbDL3RESET DSP~LINK3 RegisterID Register VME A24 Status Register HintaHintb HintcVME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset