Spectrum Brands C6x VME64 manual Vstatus Register

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Spectrum Signal Processing	Monaco Technical Reference
	Registers

VSTATUS Register

Address: 016D 8000h

D31..							..D24

			Reserved

D23..							..D16

			Reserved

D15	D14	D13	D12	D11	D10	D9	D8

	Reserved			VINTD	VINTC	VINTB	VINTA

D7	D6	D5	D4	D3	D2	D1	D0

BUSERRD	BUSERRC	BUSERRB	BUSERRA	KAVEC	/KIPL2	/KIPL1	/KIPL0

This register is used by a processor to identify the source of an INT4 interrupt.

	VINTD	Status of the user defined interrupt to node D. Set to “1” when another
		processor has set the VINTD interrupt register. Active High.

	VINTC	Status of the user defined interrupt to node C. Set to “1” when another
		processor has set the VINTC interrupt register. Active High.

	VINTB	Status of the user defined interrupt to node B. Set to “1” when another
		processor has set the VINTB interrupt register. Active High.

	VINTA	Status of the user defined interrupt to node A. Set to “1” when another
		processor has set the VINTA interrupt register. Active High.

	BUSERRD	Status of the last bus cycle access made to the SCV64 by node D, including
		SCV64 register and VME master accesses. Set to “1” if there was an error.
		Cleared by writing“80h” to the VSTATUS register. All other interrupts are
		cleared when the source of the interrupt is cleared. This interrupt is cleared
		on reset.

	BUSERRC	Status of the last bus cycle access made to the SCV64 by node C, including
		SCV64 register and VME master accesses. Set to “1” if there was an error.
		Cleared by writing“40h” to the VSTATUS register. All other interrupts are
		cleared when the source of the interrupt is cleared. This interrupt is cleared
		on reset.

	BUSERRB	Status of the last bus cycle access made to the SCV64 by node B, including
		SCV64 register and VME master accesses. Set to “1” if there was an error.
		Cleared by writing “20h” to the VSTATUS register. All other interrupts are
		cleared when the source of the interrupt is cleared. This interrupt is cleared
Part Number 500-00191		47
Revision 2.00

Image 59

Contents Monaco Revision Iii PrefaceHistory Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction PEM InterfacesVME PMCReference Documents General Bus Architecture On-Board Power SupplySysreset Reset ConditionsVME A24 Slave Interface Reset Jtag ResetBoard Layout Board LayoutOUT Jumper settingsJumper Settings Description Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressHost Port Synchronous Burst SramSynchronous Dram Processor Expansion ModuleProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus MemoryBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aSCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend KiplencDSP~LINK3 Register DL3RESETID Register Hintc VME A24 Status RegisterHinta HintbVME A24 Control Register Registers Monaco67 SpecificationsBoard Identification MonacoGeneral Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset