Spectrum Brands C6x VME64 manual Address Strobe Control Mode, Astrben

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Monaco Technical Reference	Spectrum Signal Processing
DSP~LINK3 Interface

Table 10 DSP~LINK3 Data Transfer Operating Modes

	Base	ASTRB_EN
Mode	Address	Bit	Description

Standard	0160 0000h	x	For slave boards that are similar to DSP~LINK1
Access			slave boards and operate with a fixed access
			time.

Standard	0164 0000h	0	For DSP~LINK3 slave boards that have fast,
Fast			fixed access time. This memory space is
Access			shared with the Address Strobe Control
			operating mode.
Address	0164 0000h	1	For slave boards that require more than the
Strobe			16 KWords of addressing provided by the
Control			standard DSP~LINK3 address lines. The bus
			master uses the /ASTRB cycle to place the
			page address onto the DSP~LINK3 data lines.
			It determines which address page is accessed
			on the slave board. This allows access to up to
			214 address pages with each address page
			having an address depth of 214. The /ASTRB
			Cycle has the same timing as the Standard
			Fast transfer cycle.

Ready	0168 0000h	x	For DSP~LINK3 slave boards that require
Control			variable length access times. /DSTRB is active
Access			until the slave asserts the DSP~LINK3 ready
			signal (/RDY) to end the cycle.

5.2.Address Strobe Control Mode

The Address Strobe Control mode uses the same node A 64K address space as the Standard Fast Access mode. The Address Strobe Control mode is enabled for this space by setting bit D1, the ASTRB_EN bit, of the DSP~LINK3 register to “1”. This register is located at address 016D 8018h of node A. Standard Fast Access mode writes will now generate /ASTRB cycles. The DSP~LINK3 slave attached to the Monaco board should then latch the lower addresses.

30	Part Number 500-00191
	Revision 2.00

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Contents Monaco Revision Preface IiiDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PMC InterfacesVME PEMReference Documents On-Board Power Supply General Bus ArchitectureJtag Reset Reset ConditionsVME A24 Slave Interface Reset SysresetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor NodesProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and DProcessor Expansion Module Synchronous Burst SramSynchronous Dram Host PortProcessor Booting Processor Boot Source Jumpers NodeSerial Port Routing Serial Port RoutingPEM Connections for Serial Port 0 VME and PMC Connections for Serial PortMemory Global Shared Bus Access Source TargetGlobal Shared Bus ArbitrationSingle Cycle Bus Access Burst Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave InterfaceA24 Secondary Interface Memory Map HPI Register Addresses VME address HpiaMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating ModesAddress Strobe Control Mode AstrbenInterface Signals DSP~LINK3 ResetDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value InitializeBCC2A Hurricane Implementation PCI DeviceJtag Debugging Jtag ChainJtag Debugging Interrupt Handling OverviewDSP~LINK3 Interrupts to Node a Interrupt RoutingHurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 InterruptKipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0Bus Error Interrupts Bit Node Whose Access Caused the Bus ErrorInter-processor Interrupts VME Host Interrupts To Any NodeRegister Address Summary Access Privilege Bus RegistersVpage Register KFC2..0 KSIZE1..0 KADDR1..0Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend KiplenbDL3RESET DSP~LINK3 RegisterID Register Hintb VME A24 Status RegisterHinta HintcVME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67Specifications Parameter GeneralData Access/Transfer Performance Performance and Data ThroughputSpecifications Connector Pinouts Connector LayoutVME Connectors VME P1 Connector PinoutVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 PinoutPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector PinoutPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register InitializationSCV64 Register Initialization Index VMEInterrupts to node A, 40 register Reset Jtag Sysreset